Switching-behavior improvement of insulated gate-controlled devices

Musumeci, S.; Raciti, A.; Testa, A.; Galluzzo, A.; Melito, M.

doi:10.1109/63.602559

Cited by 80 publications

(24 citation statements)

References 3 publications

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“…This is the reason why the layout should be realized with very short and symmetric connections for the two devices. In the present paper the analysis of the effect of the stray inductances in the switching behavior is not dealt [12].…”

Section: D) Considerations On the Gate Driver Circuitmentioning

confidence: 97%

Parallel connection of super-junction MOSFETs in a PFC application

Chimento

Raciti

Cannone

et al. 2009

2009 IEEE Energy Conversion Congress and Exposition

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The paper deals with an experimental analysis on the behavior of parallel connections of super-junction power MOSFET devices in a boost converter used as power factor corrector (PFC). The main impact of the parameter variation on the parallel connection has been treated. The experimental evaluation of the current sharing in parallel connection has been carried out in several operative conditions by considering the influence of different parameters. Finally, a specific arrangement able to reduce the current imbalance of the devices has been experimented and discussed.

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Section: D) Considerations On the Gate Driver Circuitmentioning

confidence: 97%

Parallel connection of super-junction MOSFETs in a PFC application

Chimento

Raciti

Cannone

et al. 2009

2009 IEEE Energy Conversion Congress and Exposition

Self Cite

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“…Switching transition control by controlling the gate current has been proposed in [16]- [18]. During the voltage rise interval of the turn-off transition, the gate of an Insulated gate (IG) PSD is charged by maximum current.…”

Section: B State Of the Art Work On Switching Transition Controlmentioning

confidence: 99%

Closed-loop control of switching transition of SiC MOSFETs

Riazmontazer

Rahnamaee

Mojab

et al. 2015

2015 IEEE Applied Power Electronics Conference and Exposition (APEC)

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This paper presents a novel closed-loop active-gatecontrol (AGC) circuit for high-voltage SiC MOSFETs, used in the high-voltage, high-frequency and high-power-density applications. The proposed controller independently adjusts the switching di/dt and dv/dt by closed-loop control of the gate current and enables one to reach optimal performance in terms of loss, device stress, and EMI. The di/dt is adjusted to control the overvoltage stress and peak reverse recovery current while the dv/dt is adjusted to control the common mode (CM) noise and switching loss. The dv/dt is the primary source of the common mode noise in power electronics converters. Dynamic control of switching dv/dt has been somewhat overlooked in the state-of-the art works based on Si based power semiconductor devices (PSDs), and maximum achievable dv/dt is used to decrease the switching loss. However, the magnitude of generated dv/dt in the high-voltage SiC-based applications is appreciable because of the exceptionally higher switching speed of the SiC MOSFETs as compared to Si IGBTs. In contrast to other works, the proposed controller dynamically and independently controls the turn-off di/dt and dv/dt of a SiC MOSFET using closed-loop control of the gate current. Independent control of turn-off di/dt and dv/dt is achieved using a delay compensation circuit. This circuit compensates the total delay in the feedback loop and predicts the onset of transition between dv/dt and di/dt control regions. The proposed control circuit operation and advantages are presented and verified by experimental results.

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“…The SOA is dominantly defined by the collector emitter breakdown voltage during tum off. The long and short-term limit is considered the same [9]. The avalanche breakdown voltage of the IGBT is determined by the open-base, collector emitter breakdown voltage of the internal PNP bipolar transistor.…”

Section: Switching Performance Requirementsmentioning

confidence: 99%

“…Because of the adiabatic heating, the local temperature dramatically increases. As a result the device can catastrophically fail in several nanoseconds after blocking collector emitter voltage collapse [9], [14]. Practically, it is very important to understand that the IGBT must not be in avalanche mode even for a very short time, 50 to 100 ns.…”

Section: Switching Performance Requirementsmentioning

confidence: 99%