Symbolic Functional Decomposition Algorithm for FSM Implementation

Abstract

This paper presents an algorithm of symbolic functional decomposition for the implementation of finite state machines in Field Programmable Gate Array (FPGA) circuits. Unlike previous approaches to this problem, which consist of separate encoding and mapping steps, this algoritm does not pre-encode the machine's states; instead, the states are encoded gradually during every step of the functional decomposition process (used for mapping the FSM to the FPGA circuit's LUT cells). This approach guarantees high quality of the final decomposition, with better results than the ones obtained by pre-encoding the FSM's states.

Overview on Strategies and Approaches for FPGA Programming

“…The main tasks in physical design include floor planning, placement and routing and circuit extraction. The synthesis process can also be viewed in three different levels [10,20,26,[31][32][33][34][35]: a. Behaviour synthesis Behavioural synthesis allows design at higher levels of abstraction by automating the translation and optimization of a behavioural description, or high-level model, into an RTL implementation which fits in with existing design flows. This method can be selectively applied to portions of a design.…”

“…This process may be done by human or a computer assisted program. There are two common categories of the synthesis process [10,20,26,[31][32][33][34][35]: a. Behaviour to structure…”