Symmetry and induction in model checking

Abstract

With the increasing complexity of digital systems, testing of digital systems is becoming increasingly important. Perhaps, the most popular method for testing hardware is simulation. The incompleteness of simulation based testing methods has spurred the recent surge in the research on formal veri cation. In formal veri cation, one builds a precise model of the hardware under scrutiny and proves that the model satis es a speci cation of interest. For example, suppose one wants to verify that a router chip does not deadlock. In this case the user will build a precise model of the router and the speci cation will express the property of deadlock freedom. The two approaches to formal veri cation are model checking and theorem proving. In this thesis we will only discuss model checking. Most model checking procedures su er from the state explosion problem, i.e., the size of the state space of the system can be exponential in the number of state variables of the system. For certain systems, exploiting the inherent symmetry can alleviate the state-explosion problem. We discuss Model Checking procedures which exploit symmetry. Current model checkers can only verify a single state-transition system at a time. We also want to extend the model checking techniques to handle in nite families of nite-state systems. In practice, nite state concurrent systems often exhibit considerable symmetry. W e i n v estigate techniques for reducing the complexity o f temporal logic model checking in the presence of symmetry. In particular, we show that symmetry can frequently be used to reduce the size of the state space that must be explored during model checking. We also investigate complexity o f v arious problems related to exploiting symmetry in model checking. Partial order based reduction techniques exploit independence of actions. We demonstrate that partial order and symmetry based reduction techniques can be applied simultaneously. The ability to reason automatically about entire families of similar state-transition systems is an important research goal. Such families arise frequently in the design of reactive systems in both hardware and software. The in nite family of token rings is a simple example. More complicated examples are trees of processes consisting of one root, several internal and leaf nodes, and hierarchical buses with di erent n umbers of processors and caches. A technique for verifying entire families of state-transition systems based on network grammars and process invariants is presented here.

State-rich model checking

“…The main disadvantage lies in the fact that finding families of processes is normally an undecidable procedure, and is hence harder to automate. An interesting discussion of the use of symmetry and induction techniques for classical model checking is given in [18]. More details about induction can also be found in [63,Chap.…”

“…In [3] a CTL model checker that is based on exploiting modularity is presented. An example of the use of symmetry and induction to enable industrial-scale case studies is given in [18]. Hardware circuits were checked using CTL in [13].…”

$$\mathsf {SceneChecker}$$: Boosting Scenario Verification Using Symmetry Abstractions

“…Related Work. The idea of using symmetries to accelerate verification has been exploited in a number of contexts such as probabilistic models [15,16], automata [17,18], distributed architectures [19], and hardware [20,21]. Some symmetry utilization algorithms are implemented in Murφ [22] and Uppaal [23].…”