Symmetry in temporal logic model checking

Abstract

Temporal logic model checking involves checking the state-space of a model of a system to determine whether errors can occur in the system. Often this involves checking symmetrically equivalent areas of the state-space. The use of symmetry reduction to increase the efficiency of model checking has inspired a wealth of activity in the area of model checking research. We provide a survey of the associated literature.

A Quantitative Analysis of Collision Resolution Protocol for Wireless Sensor Network

“…As the number of nodes increases in the protocol, the reachable state space grows exponentially. The identical nodes induce symmetry in the reachable state space which leads to redundant search over equivalent areas of the state space during model checking [15].…”

Symmetries in Modal Logics

“…In modal logics, research has been done on how to exploit symmetries in model checking for the temporal logic LTL [21,31,32,33], and for some temporalepistemic logics [34]. However, to the best of our knowledge, the use of symmetries in satisfiability and automated theorem proving for modal logics remains largely unexplored.…”

Language-Level Symmetry Reduction for Probabilistic Model Checking

“…Symmetry reduction techniques for model checking were originally proposed in [1], [2], [3] and have been studied extensively since (see [4] for a survey). The use of generic representatives in model checking was proposed in [5] and extended in [6], [16].…”

“…In this paper, we consider symmetry reduction [1], [2], [3], [4], which exploits the presence of replication in a system. Symmetry is in fact prevalent in many of the application domains to which probabilistic model checking has already proved valuable, e.g.…”