SYNAPSE—A neurocomputer that synthesizes neural algorithms on a parallel systolic engine

Ramacher, Ulrich

doi:10.1016/0743-7315(92)90070-4

Cited by 70 publications

(11 citation statements)

References 1 publication

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“…In a conventional ring structure [26], the on-chip interconnects are all local, spikes propagate serially, and spike collisions are eliminated. Since there are no spike collisions, no arbitration is needed, fan-out is low, and the local wire capacitance does not grow with the network size.…”

Section: A Two-layer Sparse Spiking Neural Networkmentioning

confidence: 99%

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

Knag

Kim

Chen

et al. 2015

IEEE J. Solid-State Circuits

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Hardware-based computer vision accelerators will be an essential part of future mobile devices to meet the low power and real-time processing requirement. To realize a high energy efficiency and high throughput, the accelerator architecture can be massively parallelized and tailored to vision processing, which is an advantage over software-based solutions and general-purpose hardware. In this work, we present an ASIC that is designed to learn and extract features from images and videos. The ASIC contains 256 leaky integrate-and-fire neurons connected in a scalable two-layer network of 8 8 grids linked in a 4-stage ring. Sparse neuron activation and the relatively small grid keep the spike collision probability low to save access arbitration. The weight memory is divided into core memory and auxiliary memory, such that the auxiliary memory is only powered on for learning to save inference power. High-throughput inference is accomplished by the parallel operation of neurons. Efficient learning is implemented by passing parameter update messages, which is further simplified by an approximation technique. A 3.06 mm 65 nm CMOS ASIC test chip is designed to achieve a maximum inference throughput of 1.24Gpixel/s at 1.0 V and 310 MHz, and on-chip learning can be completed in seconds. To improve the power consumption and energy efficiency, core memory supply voltage can be reduced to 440 mV to take advantage of the error resilience of the algorithm, reducing the inference power to 6.67 mW for a 140 Mpixel/s throughput at 35 MHz.Index Terms-Feature extraction, hardware acceleration, neural network architecture, sparse coding, sparse and independent local network.

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Section: A Two-layer Sparse Spiking Neural Networkmentioning

confidence: 99%

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

Knag

Kim

Chen

et al. 2015

IEEE J. Solid-State Circuits

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“…To keep the pipeline full, several input vectors should undergo the distance computation step before the first result becomes available and the update phase can take place. For instance, this batch approach is exploited to implement the dot-product calculation in multilayer perceptrons (MLP's) on the SYNAPSE-1 system [21]. The on-line nature of the original algorithm prevented the designers from applying the same technique to Kohonen's selforganizing maps, therefore wasting some of the potential of the machine.…”

Section: Version Winner Selection Weight Updatementioning

confidence: 99%

Modified self-organizing feature map algorithms for efficient digital hardware implementation

Ienne

Thiran

Vassilas

1997

IEEE Trans. Neural Netw.

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This paper describes two variants of the Kohonen's self-organizing feature map (SOFM) algorithm. Both variants update the weights only after presentation of a group of input vectors. In contrast, in the original algorithm the weights are updated after presentation of every input vector. The main advantage of these variants is to make available a finer grain of parallelism, for implementation on machines with a very large number of processors, without compromising the desired properties of the algorithm. In this work it is proved that, for one-dimensional (1-D) maps and 1-D continuous input and weight spaces, the strictly increasing or decreasing weight configuration forms an absorbing class in both variants, exactly as in the original algorithm. Ordering of the maps and convergence to asymptotic values are also proved, again confirming the theoretical results obtained for the original algorithm. Simulations of a real-world application using two-dimensional (2-D) maps on 12-D speech data are presented to back up the theoretical results and show that the performance of one of the variants is in all respects almost as good as the original algorithm. Finally, the practical utility of the finer parallelism made available is confirmed by the description of a massively parallel hardware system that makes effective use of the best variant.

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“…General purpose processors are used to implement widely known ANN types. VLSI-integrated circuits or special purpose processors are used for special purpose ANN's where high speed and intensive calculations are required [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Neural network training based on FPGA with floating point number format and it’s performance

Çavuşlu¹,

Karakuzu

Şahin

et al. 2010

Neural Comput & Applic

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In this paper, two-layered feed forward artificial neural network's (ANN) training by back propagation and its implementation on FPGA (field programmable gate array) using floating point number format with different bit lengths are remarked based on EX-OR problem. In the study, being suitable with the parallel data-processing specification on ANN's nature, it is especially ensured to realize ANN training operations parallel over FPGA. On the training, Virtex2vp30 chip of Xilinx FPGA family is used. The network created on FPGA is coded by using VHDL. By comparing the results to available literature, the technique developed here proved to consume less space for the subjected ANN training which has the same structure and bit length, it is shown to have better performance.

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SYNAPSE—A neurocomputer that synthesizes neural algorithms on a parallel systolic engine

Cited by 70 publications

References 1 publication

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

Modified self-organizing feature map algorithms for efficient digital hardware implementation

Neural network training based on FPGA with floating point number format and it’s performance

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