Synchronization reliability in CMOS technology

Flannagan, S.T.

doi:10.1109/jssc.1985.1052405

Cited by 32 publications

(3 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example in ASIC design, sizing is primarily driven by setup and hold time considerations. On the other hand device size optimization with respect of metastable parameters leads to different aspect ratios [4]. Both sizing schemes are considered in this paper.…”

Section: Metastability Simulation Considerationsmentioning

confidence: 99%

Impact of technology scaling on metastability performance of CMOS synchronizing latches

Baghini¹,

Desai²

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

View full text Add to dashboard Cite

show abstract

Section: Metastability Simulation Considerationsmentioning

confidence: 99%

Impact of technology scaling on metastability performance of CMOS synchronizing latches

Baghini¹,

Desai²

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

View full text Add to dashboard Cite

show abstract

“…1. Furthermore, transmission conductance of CMOS gate is independent of the number of inputs, and is approximately equal to the inverse of current amplification rate of MOSFET that functions at the oversaturation domain [9]. So, g = g3 = g4g', and (gg3g4)/g'4 in the right-hand side is approximately equal to 1.…”

Section: )mentioning

confidence: 99%

“…Generally speaking, positive feedback closed loop (called closed loop) is formed in the circuit when MS operation occurs. And, MS operation duration time increase rate can be approximatedby geometrical mean (called G-C mean) of the ratio of output capacitance and transmission conductance for all gates in the closed loop [9]. In the Circuit of Fig.…”

Section: Principle Of Shortening Metastable Operation Duration Timementioning

confidence: 99%

A method of shortening metastable operation duration time by the use of feedback

Sato

Okamoto

Sugiyama

et al. 1996

Systems & Computers in Japan

View full text Add to dashboard Cite

If metastable operation (MS operation) m u r s in conflict-resolving circuits, propagation delay time of flip-flop (FF) increases by the amount of its duration time and a malfunction may occur. This paper proposes a method of shortening duration time of MS operation that occurs when two inputs of RSFF consisting of CMOS NAND gates are switched from logic 0 to 1 approximately at the same instant. The MS operation is detected and fed back to inputs so that it is forced to terminate. A configuration of RSFF that has feedback based on this idea is first presented, and then a principle of shortening MS operation duration time follows. Then, considering implementation of RSFF by n-well process, feedback connection and MOSFET parameters are optimized. Although hardware increases slightly by addition of feedback, the result shows the MS operation duration time increase rate against input phase difference (switching time difference of two inputs of RSFF), and the range of input phase difference for MS operation incidence are reduced by ap-proximately 114 and 113, respectively, compared with conventional methods.

show abstract

Fault Modeling

Tewksbury

1989

The Kluwer International Series in Engineering and Computer Science

View full text Add to dashboard Cite

Synchronization reliability in CMOS technology

Cited by 32 publications

References 10 publications

Impact of technology scaling on metastability performance of CMOS synchronizing latches

Impact of technology scaling on metastability performance of CMOS synchronizing latches

A method of shortening metastable operation duration time by the use of feedback

Fault Modeling

Contact Info

Product

Resources

About