Synchronizing large VLSI processor arrays

Abstract

Highly parallel VLSI computing structures consist of many processing elements operating simultaneously. In order for such processing elements to communicate among themselves, some provision must be made for synchronization of data transfer. The simplest means of synchronization is the use of a global clock. Unfortunately, large clocked systems can be difficult to implement because of the inevitable problem of clock skews and delays, which can be especially acute in VLSI systems as feature sizes shrink. For the near term, good engineering and technology improvements can be expected to maintain the feasibility of clocking in such systems; however, clock distribution problems crop up in any technology as systems grow. An alternative means of enforcing necessary synchronization is the use of self-timed, asynchronous schemes, at the cost of increased design complexity and hardware cost. Realizing that different circumstances call for different synchronization methods, this paper provides a spectrum of synchronization models; based on the assumptions made for each model, theoretical lower bounds on clock skew are derived, and appropriate or best-possible synchronization schemes for large processor arrays are proposed. One set of models is based on assumptions that allow the use of a pipelined clocking scheme, where more than one clock event is propagated at a time. In this case, it is shown that even assuming that physical variations along clock lines can produce skews between wires of the same length, any one-dimensional processor array can be correctly synchronized by a global pipelined clock while enjoying desirable properties such as modularity, expandability and robustness. This result cannot be extended to two-dimensional arrays, however—the paper shows that under this assumption, it is impossible to run a clock such that the maximum clock skew between two communicating cells will be bounded by a constant as systems grow. For such cases or where pipelined clocking is unworkable, a synchronization scheme incorporating both clocked and “asynchronous” elements is proposed.

Efficient Translation of Algorithmic Kernels on Large-Scale Multi-cores

“…The first assumption is justified because the individual µ-cores are small and compact in size, and the only interconnection required is with their nearest neighbors. The assumption of clock scalability may be critical for large MMC arrays, however, relevant research has been done in related areas [4], [10] which can be adapted to achieve clock synchronization for large MMC arrays. The implementation was accomplished using the Simulink tool which served as a great aid for efficient implementation and visual representation.…”

“…100% (3,2) 80% (3,3) 56% (4,1) 90% (4,2) 10% (4,3) 34% (1,4) 100% (2,4) 90% (3,4) 65% (4,4) 99% Fig. 3.…”

“…2) Input/Output Instructions: The µ-core processor has four input and four output ports corresponding to the East, West, (1,1) a0 (1,2) b4 (1,3) c0 (1,4) 0a (2,1) b0 (2,2) d4 (2,3) c5 (2,4) 2a (3,1) e0 (3,2) ba (3,3) ca (3,4) 3a (4,1) f0 (4,2) 00 (4,3) 10 (4,4) 02 (a) (1,1) b4 (1,2) c0 (1,3) 0a (2,1) d4 (2,2) c5 (2,3) 2a (3,1) ba (3,2) ca (3,3) 3a (4,1) 00 …”

“…3. Routing data from µ-core (1,1) to (4,3) between the bit fields in a micro-instruction and the control signals sent to the various parts of the CPU, allowing for a simple design for the control-decoding logic. A translation of macro-instructions for the MMC array to micro-instructions for individual cores is required to facilitate mapping of algorithms to the MMC array.…”

Comparison of tree and straight-line clocking for long systolic arrays

“…One of the limiting factors in building long pipelines is the difficulty in achieving proper and reliable synchronization [5], [ 10], [11 ]. In this paper we investigate clock synchronization failures in such systems, in terms of their length and parameters that characterize clocking circuitry, such as delays in buffers and wires, and variance in buffer response time.…”