Synchronous Game Semantics via Round Abstraction

Ghica, Dan R.; Menaa, Mohamed N.

doi:10.1007/978-3-642-19805-2_24

Cited by 5 publications

(10 citation statements)

References 20 publications

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“…The protocol above is asynchronous, and for the purpose of hardware synthesis we use a low-latency representation called round-abstraction [Ghica and Menaa, 2011], allowing multiple inputs and outputs on the same transition while avoiding deadlocks and race conditions, as in Fig. 8.…”

Section: Enforcing Programming Language Abstractionsmentioning

confidence: 99%

Coherent Minimisation: Towards efficient tamper-proof compilation

Ghica

Al-Zobaidi

2012

Electron. Proc. Theor. Comput. Sci.

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Automata representing game-semantic models of programs are meant to operate in environments whose input-output behaviour is constrained by the rules of a game. This can lead to a notion of equivalence between states which is weaker than the conventional notion of bisimulation, since not all actions are available to the environment. An environment which attempts to break the rules of the game is, effectively, mounting a low-level attack against a system. In this paper we show how (and why) to enforce game rules in games-based hardware synthesis and how to use this weaker notion of equivalence, called coherent equivalence, to aggressively minimise automata

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Section: Enforcing Programming Language Abstractionsmentioning

confidence: 99%

Coherent Minimisation: Towards efficient tamper-proof compilation

Ghica

Al-Zobaidi

2012

Electron. Proc. Theor. Comput. Sci.

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“…In this paper we are interested in compiling SCI to sequential hardware; the GoS method relies essentially on the existence of a game-semantic model for the programming language. The existing game [Wal04] and game-like [McC10] models of SCI are asynchronous, and using them to create synchronous hardware raises some technical challenges, which are addressed in previous work on round abstraction [GM10,GM11].…”

Section: Syntactic Control Of Interferencementioning

confidence: 99%

“…Below, for each language constant we will give the asynchronous game-semantic interpretation and its low-latency synchronous representation [GM11] and the (obvious) circuit implementation. For the purpose of giving the game-semantics and its representation, the circuit interface will correspond to the set of moves; the semantics is a set of traces over the possible moves.…”

Section: Syntactic Control Of Interferencementioning

confidence: 99%

“…Note the unit delay placed between the command acknowledgment and the expression request. Its presence is a necessary artifact of correctly representing asynchronous processes synchronously and cannot be optimised away [GM11].…”

Section: Sequential Compositionmentioning

confidence: 99%

“…Except for recursion, the implementation of the compiler is a hardware instantiation of the synchronous representation of the game semantics and is correct by construction as explained in a series of papers [McC02,GM10,GM11]. The detailed proof of correctness of the fix-point constructor is beyond the scope of this paper, but the step-by-step construction given in this section mirrors the structure of the proof of correctness.…”

Section: Case Studiesmentioning

confidence: 99%

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Geometry of synthesis iv

Ghica¹,

Smith²,

Singh³

2011

Proceedings of the 16th ACM SIGPLAN International Conference on Functional Programming

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Abramsky's Geometry of Interaction interpretation (GoI) is a logical-directed way to reconcile the process and functional views of computation, and can lead to a dataflow-style semantics of programming languages that is both operational (i.e. effective) and denotational (i.e. inductive on the language syntax). The key idea of Ghica's Geometry of Synthesis (GoS) approach is that for certain programming languages (namely Reynolds's affine Syntactic Control of Interference-SCI) the GoI processes-like interpretation of the language can be given a finitary representation, for both internal state and tokens. A physical realisation of this representation becomes a semantics-directed compiler for SCI into hardware. In this paper we examine the issue of compiling affine recursive programs into hardware using the GoS method. We give syntax and compilation techniques for unfolding recursive computation in space or in time and we illustrate it with simple benchmark-style examples. We examine the performance of the benchmarks against conventional CPU-based execution models.

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Function interface models for hardware compilation

Ghica¹

2011

Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011)

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The problem of synthesis of gate-level descriptions of digital circuits from behavioural specifications written in higherlevel programming languages (hardware compilation) has been studied for a long time yet a definitive solution has not been forthcoming. The argument of this essay is mainly methodological, bringing a perspective that is informed by recent developments in programming-language theory. We argue that one of the major obstacles in the way of hardware compilation becoming a useful and mature technology is the lack of a well defined function interface model, i.e. a canonical way in which functions communicate with arguments. We discuss the consequences of this problem and propose a solution based on new developments in programming language theory. We conclude by presenting a prototype implementation and some examples illustrating our principles.

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Synchronous Game Semantics via Round Abstraction

Cited by 5 publications

References 20 publications

Coherent Minimisation: Towards efficient tamper-proof compilation

Coherent Minimisation: Towards efficient tamper-proof compilation

Geometry of synthesis iv

Function interface models for hardware compilation

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