Synchronous handshake circuits

Elastic systems provide tolerance to the variations in computation and communication delays. The incorporation of elasticity opens new opportunities for optimization using new correct-by-construction transformations that cannot be applied to rigid non-elastic systems.The basics of synchronous and asynchronous elastic systems will be reviewed. A set of behavior-preserving transformations will be presented: retiming, recycling, early evaluation, variablelatency units and speculative execution. The application of these transformations for performance and power optimization will be discussed. Finally, a novel framework for microarchitectural exploration will be introduced, showing that the optimal pipelining of a circuit can be automatically obtained by using the previous transformations.

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“…This protocol is similar to the one presented in [24], [34] and it is conceptually similar, but not equivalent, to the one presented in [12].…”

Section: A a Synchronous Elastic Protocolmentioning

confidence: 61%

Elastic systems

Cortadella

Galceran-Oms

Kishinevsky

2010

Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)

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“…This backend maps a circuit described in Haste into a net-list of clocked handshake components [25]. The resulting circuits are similar to the above mentioned latency insensitive and synchronous elastic systems, but there is also one important difference: they are control driven (using passive variables) rather than data driven.…”

Section: Synchronous Handshake Componentsmentioning

confidence: 99%

Current trends in high-level synthesis of asynchronous circuits

Sparsø

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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Abstract-This paper is a survey paper presenting what the author sees as two major and promising trends in the current research in CAD-tools and design-methods for asynchronous circuits. One branch of research builds on top of existing asynchronous CAD-tools that perform syntax directed translation, e.g. the Haste/TiDE tool from Handshake Solutions or the Balsa tool from the University of Manchester. The aims are to add highlevel synthesis capabilities to these tools and to extend the tools such that a wider range of (higher speed) micro-architectures can be generated. Another branch of research takes a conventional synchronous circuit as the starting point, and then adds some form of handshake-based flow-control. One approach keeps the global clock and implements discrete-time asynchronous operation. Another approach substitutes the clocked registers by asynchronous handshake-registers, thus creating truly continuoustime asynchronous circuits that operate without a clock. The perspective here is that the substitution/conversion is done as the final step in an otherwise conventional synchronous design flow.

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“…In general, the idea of clocking an asynchonrous circuit is not new. [16] presents a synchronous back-end for the Tangram compiler with two aims: (i) providing a fast approach for prototyping asynchronous circuits using synchronous FPGAs, and (ii) reducing the risk of adoption of asynchonrous design methodology in industry by supporting the synchronous mode of execution as a fall-back scenario. [17] introduced a systematic approach for testing and debugging of asynchonrous circuits by incorporating conventional synchronous scanchains.…”

Section: B Related Workmentioning

confidence: 99%

Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools

Tarawneh

Mokhov

2018

2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

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Asynchronous circuits are pervasive in modern synchronous systems, but they are still designed and verified in isolation, using dedicated asynchronous design flows, formalisms and tools. We describe a method to verify gate-level asynchronous circuit implementations using formal verification tools and property languages for synchronous logic. We report observations and findings from applying this method to use case designs using an industrial and an open source formal verification tools for synchronous logic (Cadence Incisive Formal and Xprova), and compare performance and verification capabilities against two verification tools for asynchronous circuits. Finally, we discuss the advantages and practical considerations of bridging synchronous logic verification tools to the domain of asynchronous circuits. Our main conclusion is that, while there are performance penalties, there is still significant value in enabling users to verify asynchronous circuits using tools that may be more familiar, trusted or more widely adopted.

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Synchronous handshake circuits

Abstract: Abstract

Cited by 18 publications

References 16 publications

Elastic systems

Elastic systems

Current trends in high-level synthesis of asynchronous circuits

Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools

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