Synchroscalar

Oliver, John; Rao, Ravishankar; Sultana, Paul; Crandall, Jedidiah R.; Czernikowski, Erik; Jones, Leslie Webber; Franklin, Diana; Akella, Venkatesh; Chong, Frederic T.

doi:10.1145/1028176.1006714

Cited by 20 publications

(1 citation statement)

References 17 publications

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“…As shown in Figure 1, the ACCESA configuration architecture for FPGA is designed to be modular and block based, to facilitate efficient power management and customizable QoS provisions per module during run-time partial reconfiguration. In reference [4] their "Synchroscalar" architecture is column based, but here a block based configuration architecture has been designed for modern FPGAs like Xilinx's Virtex-4 and Virtex-5 etc. [5], [6], [7], [8], where block based partial reconfiguration is possible.…”

Section: Accesa Architecturementioning

confidence: 99%

A Communication-Centric Embedded System Architecture (ACCESA)

Guha

2009

2009 First International Conference on Computational Intelligence, Communication Systems and Networks

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In the era of application convergence, the embedded systems are required to support multiple applications with different traffic patterns and Quality of Service (QoS) requirements. But continual process technology's shrinking trend makes the communication network of the embedded system the performance bottleneck for its increased latency. To ameliorate this problem, a communication-centric embedded system architecture (ACCESA) is proposed in this paper which is modular and block based. The modular and block based architecture of ACCESA helps in performance improvement of the embedded system by means of flexible and efficient QoS provisions and power management. The pre-fabricated or preconfigured hybrid and hierarchical communication network of ACCESA saves on run-time reconfiguration time and on interconnect cost by preventing under utilization of communication resources without sacrificing on processing speed and throughput of the applications. This reduced and efficient resource usage in ACCESA in turn saves on power consumption of the chip.

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Section: Accesa Architecturementioning

confidence: 99%

A Communication-Centric Embedded System Architecture (ACCESA)

Guha

2009

2009 First International Conference on Computational Intelligence, Communication Systems and Networks

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Integrated CPU Cache Power Management in Multiple Clock Domain Processors

AbouGhazaleh

Childers

Mossé

et al.

High Performance Embedded Architectures and Compilers

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Abstract. Multiple clock domain (MCD) chip design addresses the problem of increasing clock skew in different chip units. Importantly, MCD design offers an opportunity for fine grain power/energy management of the components in each clock domain with dynamic voltage scaling (DVS). In this paper, we propose and evaluate a novel integrated DVS approach to synergistically manage the energy of chip components in different clock domains. We focus on embedded processors where core and L2 cache domains are the major energy consumers. We propose a policy that adapts clock speed and voltage in both domains based on each domain's workload and the workload experienced by the other domain. In our approach, the DVS policy detects and accounts for the effect of inter-domain interactions. Based on the interaction between the two domains, we select an appropriate clock speed and voltage that optimizes the energy of the entire chip. For the Mibench benchmarks, our policy achieves an average improvement over nopower-management of 15.5% in energy-delay product and 19% in energy savings. In comparison to a traditional DVS policy for MCD design that manages domains independently, our policy achieves an 3.5% average improvement in energy-delay and 4% less energy, with a negligible 1% decrease in performance. We also show that an integrated DVS policy for MCD design with two domains is more energy efficient for simple embedded processors than high-end ones.

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