Synergy of synthesis and test (logic design)

Abstract

This paper presents an integrated, compiler-driven approach to digital chip design that automates scan-based design and test pattern generation for 100% stuck-at fault coverage. The approach combines language-based design capture, logic synthesis and test pattern generation; and it is especially well suited for designs where reducing design time is more important than minimizing silicon area. The necessary research and development associated with the systenl was highly leveraged by joint cooperative efforts of a multidisciplined team, combining both industrial and institutional perspectives. Synthesis of Boolean equatlons into standard cell modules using logic rninimization[6,7], decomposition and factoring[8], and technology mapping[9]. 3. Netlist audit for conformance to scan-based design rules[lO], followed by automatic test pattern generation (ATPG)[11,12] and a boundary scan implementation[l3]. Redundancy removal techniques[lO] are a natural by-product of ATPG. The ATPG program was recently extended to work on hierarchical designs[l4]. 4. Standard cell placement, routing and chip layout[l5].