Synthesis and Optimization of Multilevel Logic under Timing Constraints

Bartlett, K.; Cohen, William A.; Geus, Aart de; Hachtel, Gary D.

doi:10.1109/tcad.1986.1270229

Cited by 74 publications

(15 citation statements)

References 7 publications

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“…16. With reference t o Problem 13, suppose xlx2x', + x1xt2x; is the ON-set of an incompletely specified function (i.e., f ) and that ~1 x 2 Notice that these f and d are those of the previous problem.…”

Section: Solutionmentioning

confidence: 99%

Logic Synthesis and Verification Algorithms

1996

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Section: Solutionmentioning

confidence: 99%

Logic Synthesis and Verification Algorithms

1996

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“…A work of milestone importance is [6], where the notions of kernels was introduced and a method for fast algebraic decomposition based on kernels was developed. This technique with minor modifications are used in [56,57,58,53,59,3]. Techniques for conjunctive decomposition can be found in [22,21].…”

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confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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KTH School of Information andCommunication Technology SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektronik fredagen den 26 januari 2007 klockan 9.00 i Sal E, Forumhuset, Kungl Tekniska högskolan, Isafjordsgatan 39, Kista. © Petra Färm, januari 2007Tryck: Universitetsservice US AB iii Abstract A conventional logic synthesis flow is composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions.We present a global optimization approach combining technology independent optimization steps with technology dependent objectives in an annealing-based framework. We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution. Furthermore, we show that the presented approach can smoothly trade-off complex, multiple-dimensional objective functions and achieve competitive results. The combination of technology independent and technology dependent objectives is handled through dynamic weighting. Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels. The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework can be applied to two emerging technologies, chemically assembled nanotechnology and molecule cascades. New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices. Alternatives to silicon VLSI have been proposed, including techniques based on molecular electronics, quantum mechanics, and biological processes. We are hoping that our research in how to apply our developed logic synthesis framework to two of the emerging technologies might provide useful information for other designers moving in this direction.iv

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“…Some of the rule based techniques are LSS [13] and SOCRATES [15]. These use predefined set of local transformations based on design style and technology to improve delay.…”

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Timing driven gate duplication

Srivastava

Kastner

Chen

et al. 2004

IEEE Trans. VLSI Syst.

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Abstract-In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary inputs(PI) in topologically sorted order evaluating tuples at the input pins of gates. The tuple's first component corresponds to the input pin required time if that gate is not duplicated. The second component corresponds to the input pin required time if that gate were duplicated. After tuple evaluation the algorithm traverses the network from PI to PO in topologically sorted order, deciding the gates to be duplicated. The last and final traversal is again from PO to PI, in which the gates are physically duplicated. Our algorithm uses the dynamic programming structure. We report delay improvements over other optimization methodologies. Gate duplication, along with other optimization strategies, can be used for meeting the stringent delay constraints in today's ultra complex designs.

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Synthesis and Optimization of Multilevel Logic under Timing Constraints

Cited by 74 publications

References 7 publications

Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms

Integrated logic synthesis using simulated annealing

Timing driven gate duplication

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