Synthesis of application-specific highly efficient multi-mode cores for embedded systems

Abstract

In this paper, we present a novel design methodology for synthesizing multiple configurations (or modes) into a single programmable core that can be used in embedded systems. Recent portable applications require reconfigurability of a system along with efficiency in terms of power, performance, and area. The field programmable gate arrays (FPGAs) provide a reconfigurable platform; however, they are slower in speed with significantly higher power and area than achievable by a customized application-specific integrated circuits (ASIC). Implementation of a system in either FPGA or ASIC represents a trade-off between programmability and design efficiency. In this work, we have developed techniques to realize efficient reconfigurable cores for a set of user-specified applications. The resultant system, named as multimode system, can easily switch configurations throughout the set of configurations it is designed for. A data flow graph transformation method coupled with efficient scheduling and allocation is used to automatically synthesize a Multi-Mode system from its behavior-level specifications. Experimental results on several applications demonstrate that our implementations can achieve about 60X power reduction on average and run 3.5X faster over corresponding FPGA implementations.

Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

“…This is an efficient method for reducing certain costs such as area usage, power consumption, or configuration time reduction in embedded systems and DSP applications [13][14][15].…”

Synthesis of Multimode digital signal processing systems

“…In [11] and [12], an approach that consists in unifying scheduled DFGs during the binding step has been proposed. In [11], both datapath and controller generation is presented.…”

“…Finally, the others DFGs are assigned trying to minimize hardware resource overhead. In [12], the methodology begins by the scheduling of each DFG under the given timing/resource constraints. Then the scheduled DFGs are concatenated (chained) into a single DFG.…”

Applications of Small-Scale Reconfigurability to Graphics Processors

“…Compton and Hauck have defined a testing method and quantification metric for flexibility of reconfigurable hardware [4]. Other examples of relevant research in reconfigurable hardware include Kim et al [8] and Chiou et al [2].…”