Synthesis of Approximate Combinational Circuits based on Logic Regression Approach

Stempkovsky, A. L.; Telpukhov, Dmitry; Solovyev, Roman

doi:10.1109/ewdts50664.2020.9224981

Cited by 4 publications

(2 citation statements)

References 13 publications

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“…In Stempkovsky [51], the logic learning problem is explored with logic regression technique in a flow based on two-level minimization methods. This research explores the viability of such a technique and highlights a fundamental drawback of the proposed method: the complexity of implementing circuits with many linearly non-separable elements such as XOR and XNOR functions.…”

Section: B Logic Learningmentioning

confidence: 99%

Review of Machine Learning in Logic Synthesis

Berndt

Fogaça

Meinhardt

2022

JICS

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Electronic design automation tools have multiple options that need to be tuned for specific designs and technology nodes. Traditionally, the tuning process is done by teams of expert engineers and demands a large amount of computational resources.In recent years, there has been an increased effort to apply machine learning techniques in electronic design automation problems, attempting to increase the design flow correlation and predictability, hence reducing the time spent on tuning.In this work, we revise modern approaches in electronic design automation and machine learning techniques applied during logic synthesis. We categorize and discuss their core technologies, such as transforming data into images. Machine learning techniques are as good as the available data. Thus, we present existing learning datasets for logic synthesis and strategies such as data augmentation to overcome the lack of specific data for logic synthesis problems.To cope with these problems, we discuss how research is shifting from traditional supervised learning techniques to reinforcement learning-based methods.

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Section: B Logic Learningmentioning

confidence: 99%

Review of Machine Learning in Logic Synthesis

Berndt

Fogaça

Meinhardt

2022

JICS

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“…Although this method is accurate, it is highly exhaustive in process [14,15] and hence is not a feasible solution for realizing higher-order circuits. An efficient two-level heuristic minimization scheme via a logical regression technique was investigated for structural synthesis in [24]. However, it fails to incorporate a high number of XOR and XNOR gates whenever required, especially for the accumulator and its associated system design.…”

Section: Introductionmentioning

confidence: 99%

Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP

Prashanth,

Rao

2024

IET Computers & Digital Techniques

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Unconventional functions, including activation functions and power functions, are extremely hard-to-realize primarily due to the difficulty in arriving at the hierarchical design. The hierarchical design allows the synthesis tool to map the functionality with that of standard cells employed through the regular ASIC synthesis flow. For conventional functions, the hierarchical design is structured and then supplied to the synthesis flow, whereas, for unconventional functions, the same method is not reliable, since the current synthesis method does not offer any design-space exploration scheme to arrive at an easy-to-realize design entity. The unconventional functions either take a long synthesis run-time or additional efforts are spent in restructuring the hierarchical design for the desired function to synthesizable ones. Cartesian genetic programing (CGP) allows to not only incorporate custom logic gates for synthesizing the hierarchical design but also aids in the design-space exploration for the targeted function through the custom gates. The CGP configuration evolves difficult-to-realize complex functions with multiple solutions, and filtering through desired Pareto-optimal requirements offers a unique hierarchical design. Incorporating CGP-derived hierarchical designs into the traditional synthesis flow is instrumental for implementing and evaluating higher-order designs comprising nonlinear functional constructs. Six activation functions and power functions that fall in the category of unconventional functions are realized by the CGP method using custom cells to demonstrate the capability. Further, the hierarchical design of these unconventional functions is flattened and compared with the same function that is directly synthesized using basic gates. The CGP-derived synthesis method reports 3× less synthesis time for realizing the complex functions at the hierarchical level compared to the synthesis using basic gate cells. Hardware characteristics and error metrics are also investigated for the CGP realized complex functions and are made freely available for further usage to the research and designers’ community.

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SOMALib: Library of Exact and Approximate Activation Functions for Hardware-efficient Neural Network Accelerators

Prashanth

Rao

2022

2022 IEEE 40th International Conference on Computer Design (ICCD)

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Synthesis of Approximate Combinational Circuits based on Logic Regression Approach

Cited by 4 publications

References 13 publications

Review of Machine Learning in Logic Synthesis

Review of Machine Learning in Logic Synthesis

Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP

SOMALib: Library of Exact and Approximate Activation Functions for Hardware-efficient Neural Network Accelerators

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