Synthesis of instruction sets for pipelined microprocessors

Huang, Ing-Jer; Despain, Alvin M.

doi:10.1145/196244.196250

Cited by 39 publications

(10 citation statements)

References 11 publications

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“…As the name suggests, complete customization involves the whole instruction-set which is tuned towards the requirements of an application [2,3,4,5], while partial customization involves the extension of an existing instruction-set by means of a limited number of instructions [6,7,8,9,10,11,12,13,14]. In both cases the goal is to design an Instruction-Set containing the most important operations needed by the application to maximize the performance.…”

Section: Motivationmentioning

confidence: 99%

The Instruction-Set Extension Problem: A Survey

Galuzzi

Bertels

Lecture Notes in Computer Science

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Abstract.Over the last years, we have witnessed the increased use of Application-Specific Instruction-Set Processors (ASIPs). These ASIPs are processors that have a customizable instruction-set, which can be tuned towards specific requirements. The identification, definition and implementation of those operations that provide the largest performance improvement and that should be hardwired, extending in this way the Instruction-Set, constitutes a major challenge. The purpose of this paper is to investigate and study the issues regarding the customization of an Instruction-Set in function of the specific requirements of an application. Additionally, the paper provides an overview of all relevant aspects of the problem and compensates the lack of a general view of the problem in the existing literature.

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Section: Motivationmentioning

confidence: 99%

The Instruction-Set Extension Problem: A Survey

Galuzzi

Bertels

Lecture Notes in Computer Science

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“…6 b opr must be greater or equal to lg(n r1 + n r2 ), where n r1 and n r2 are the numbers of registers in the register files RF 1 and RF 2 , respectively. If the number of registers in each register file is increased, b opr must be increased and then it must cause area increase in a processor kernel.…”

Section: Observation 2 Kernel Area Is Increased If Y-bus Is Added Depmentioning

confidence: 99%

“…Hardware/software codesign can be one of the powerful design methodologies in order to obtain an appropriate configuration for processor cores. Several hardware/software codesign systems for processor core design have been reported such as in [1]- [3], [6].…”

Section: Introductionmentioning

confidence: 99%

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Area/delay estimation for digital signal processor cores

Miyaoka¹,

Kataoka²,

Togawa³

et al.

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

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Abstract-Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2ns when comparing estimated area and delay with logic-synthesized area and delay.

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“…The work in [19] presents a technique to generate multi-cycle application specific instructions for DSP applications. Instruction set design and selection are treated as a scheduling problem in [20], and as a module selection or operation coupling problem in [11], [21]. ASIP instruction set optimization under functional unit sharing constraints is addressed in [22].…”

Section: A Related Workmentioning

confidence: 99%

Synthesis of custom processors based on extensible platforms

Sun

Ravi

Raghunathan

et al.

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.

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Abstract-Efficiency and flexibility are critical, but often conflicting, design goals in embedded system design. The recent emergence of extensible processors promises a favorable tradeoff between efficiency and flexibility, while keeping design turnaround times short. Current extensible processor design flows automate several tedious tasks, but typically require designers to manually select the parts of the program that are to be implemented as custom instructions.In this work, we describe an automatic methodology to select custom instructions to augment an extensible processor, in order to maximize its efficiency for a given application program. We demonstrate that the number of custom instruction candidates grows rapidly with program size, leading to a large design space, and that the quality (speedup) of custom instructions varies significantly across this space, motivating the need for the proposed flow. Our methodology features cost functions to guide the custom instruction selection process, as well as static and dynamic pruning techniques to eliminate inferior parts of the design space from consideration. Further, we employ a two-stage process, wherein a limited number of promising instruction candidates are first selected, and then evaluated in more detail through cycle-accurate instruction set simulation and synthesis of the corresponding hardware, to identify the custom instruction combinations that result in the highest program speedup or maximize speedup under a given area constraint.We have evaluated the proposed techniques using a state-of-theart extensible processor platform, in the context of a commercial design flow. Experiments with several benchmark programs indicate that custom processors synthesized using automatic custom instruction selection can result in large improvements in performance (upto 5.4X, average of 3.4X), energy (upto 4.5X, average of 3.2X), and energy-delay product (upto 24.2X, average of 12.6X), while speeding up the design process significantly.

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Synthesis of instruction sets for pipelined microprocessors

Cited by 39 publications

References 11 publications

The Instruction-Set Extension Problem: A Survey

The Instruction-Set Extension Problem: A Survey

Area/delay estimation for digital signal processor cores

Synthesis of custom processors based on extensible platforms

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