Synthesis of localized 2D‐layers of silicon nanoparticles embedded in a SiO₂ layer by a stencil‐masked ultra‐low energy ion implantation process

Abstract

We propose an original approach called "stencil-masked ion implantation process" to perform a spatially localized synthesis of a limited number of Si nanoparticles (nps) within a thin SiO 2 layer. This process consists in implanting silicon ions at ultra-low energy through a stencil mask containing a periodic array of opened windows (from 50 nm to 2µm). After the stencil removal, a thermal annealing is used to synthesize small and spherical embedded nps. AFM observations show that the stencil windows are perfectly transferred into the substrate without any clogging or blurring effect. The samples exhibit a 3nm localized swelling of the regions rich in Si nps. Moreover, photoluminescence (PL) spectroscopy shows that due to the quantum confinement only the implanted regions containing the Si nps are emitting light. We propose an original approach called "stencil-masked ion implantation process" to perform a spatially localized synthesis of a limited number of Si nanoparticles (nps) within a thin SiO 2 layer. This process consists in implanting silicon ions at ultra-low energy through a stencil mask containing a periodic array of opened windows (from 50 nm to 2 µm). After the stencil removal, a thermal annealing is used to synthesize small and spherical embedded nps. AFM observations show that the stencil windows are perfectly transferred into the substrate without any clogging or blurring effect. The samples exhibit a 3 nm localized swelling of the regions rich in Si nps. Moreover, photoluminescence (PL) spectroscopy shows that due to the quantum confinement only the implanted regions containing the Si nps are emitting light.

Metallic Nanowires by Full Wafer Stencil Lithography

“…An alternative method for nanopatterning is stencil lithography (SL). SL is a shadow masking technique, illustrated in Figure a, that only requires to put a stencil onto a substrate for direct and parallel pattering by deposition, etching, or implantation of the substrate through the stencil apertures without any resist processing. Compared to the previous techniques, SL has a lower resolution and the patterning area is limited by the size and stability of the membranes; nevertheless, SL has been used to pattern metallic dots <50 nm in diameter with chip size stencils , and areas up to 1 × 3 mm 2 have been patterned with 300 nm metallic dots .…”

Nanosecond pulsed laser ablated sub-10 nm silicon nanoparticles for improving photovoltaic conversion efficiency of commercial solar cells

“…There are various alternative methods for Si-NPs synthesis including pulsed laser ablation [15], chemical vapor deposition [16], ion implantation [17], electrochemical etching [18], thermal decomposition of silane [19], ball milling [20] and plasma synthesis [21]. However, high volume of ultra-small Si-NPs production is one of the most challenging issues.…”

All-stencil transistor fabrication on 3D silicon substrates

“…It also has demonstrated its applicability on non-standard substrates where conventional UV-lithography cannot be used, like delicate substrates [12], polymers [13,14] and non-planar substrates [7,15,16]. In addition, to material deposition, it has also been used to directly mask the dry etching of different materials [17][18][19] and the implantation of impurities [20][21][22]. SL has reached the status of a stable technique that can be used in 100 mm wafers and can achieve sub-100 nm resolution [23,24] even using dynamic patterning of structures [25].…”