Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip

Stuart, Matthias Bo; Stensgaard, Mikkel Bystrup; Sparsø, Jens

doi:10.1145/1629435.1629500

Cited by 7 publications

(3 citation statements)

References 16 publications

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“…This article combines and extends two of our previous articles [Stensgaard and Sparsø 2008;Stuart et al 2009]. We provide additional and more in-depth explanations and extend on the results from these previous papers.…”

Section: Introductionsupporting

confidence: 72%

The ReNoC Reconfigurable Network-on-Chip

Stuart

Stensgaard

Sparsø

2011

ACM Trans. Embed. Comput. Syst.

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This article presents a reconfigurable network-on-chip architecture called ReNoC, which is intended for use in general-purpose multiprocessor system-on-chip platforms, and which enables application-specific logical NoC topologies to be configured, thus providing both efficiency and flexibility. The article presents three novel algorithms that synthesize an application-specific NoC topology, map it onto the physical ReNoC architecture, and create deadlock-free, application-specific routing algorithms. We apply our algorithms to a mixture of real and synthetic applications and target three different physical architectures. Compared to a conventional NoC, ReNoC reduces power consumption by up to 58% on average.

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Section: Introductionsupporting

confidence: 72%

The ReNoC Reconfigurable Network-on-Chip

Stuart

Stensgaard

Sparsø

2011

ACM Trans. Embed. Comput. Syst.

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“…We assume 1-hop = 1mm in this paper from place-and-route of a Freescale PowerPC e200z7 core in 45nm. [14], [15] adds an extra topology switch (a set of muxes) at the output ports for each router and presets them to enable static routes in the network before the application is run. Skip-links [16] dynamically reconfigures the topology based on the traffic at each router when application is run, and sets up the crossbars to allow flits to bypass buffering and arbitration stages at intermediate routers.…”

Section: Introductionmentioning

confidence: 99%

SMART: A Single-Cycle Reconfigurable NoC for SoC Applications

Chen

Park

Krishna

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-As technology scales, SoCs are increasing in core counts, leading to the need for scalable NoCs to interconnect the multiple cores on the chip. Given aggressive SoC design targets, NoCs have to deliver low latency, high bandwidth, at low power and area overheads. In this paper, we propose Single-cycle Multihop Asynchronous Repeated Traversal (SMART) NoC, a NoC that reconfigures and tailors a generic mesh topology for SoC applications at runtime. The heart of our SMART NoC is a novel low-swing clockless repeated link circuit embedded within the router crossbars, that allows packets to potentially bypass all the way from source to destination core within a single clock cycle, without being latched at any intermediate router. Our clockless repeater link has been proven in silicon in 45nm SOI. Results show that at 2GHz, we can traverse 8 mm within a single cycle, i.e. 8 hops with 1 mm cores. We implement the SMART NoC to layout and show that SMART NoC gives 60% latency savings, and 2.2X power savings compared to a baseline mesh NoC.

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“…In [3], a method for synthesizing custom NoCbased interconnects given a BG is presented. In [4], BGs are used for configuring a mixed circuit-and packet-switched interconnect, while in [5], a BG is mapped onto a tile-based SoC.…”

Section: Introductionmentioning

confidence: 99%

Analytical derivation of traffic patterns in shared memory architectures from Task Graphs

Stuart

Sparsø

2009

2009 Norchip

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Abstract-Task Graphs is a commonly used application model in research in computer-aided design tools for design space exploration of embedded systems, including system synthesis, scheduling and application mapping. These design tools need an estimate of the actual communication in the target system caused by the application modelled by the task graph.In this paper, we present a method for analytically deriving the worst-case traffic pattern when a task graph is mapped to a multiprocessor system-on-chip with a shared memory architecture. We describe the additionally needed information besides the dependencies in the task graph in order to derive the traffic pattern. Finally, we construct a simulator that we use to find the actual traffic pattern in a system and compare this to the derived pattern. Results show that our worst-case derivation overestimates the bandwidth by 9% for systems with small caches and between 32% and 52% for systems with large caches.

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Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip

Cited by 7 publications

References 16 publications

The ReNoC Reconfigurable Network-on-Chip

The ReNoC Reconfigurable Network-on-Chip

SMART: A Single-Cycle Reconfigurable NoC for SoC Applications

Analytical derivation of traffic patterns in shared memory architectures from Task Graphs

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