Synthesizing SVA local variables for formal verification

Abstract

This paper describes techniques for efficiently handling a subset of SystemVerilog Assertion(SVA) safety properties with local variables in formal verification. The techniques produce checker circuits using datapath logic and pipeline registers for handling the local variables where the datapath logic and pipeline registers scales lineally to the size of the property expressed in the SVA abstract grammar.A high level specification for describing and synthesizing protocol monitors using regular expression, storage vasiables and pipeline operators is proposed in 161. A notion of dynamic threads is introduced, however, the language has different language semantics where the choice operators can't bifurcate threads compared to SVA.Recent work in SVA compilation[7l is bssed on translating SVA assertions into Blnespec constructs and uses Dluespec compiler to generate the checker circuit. Their work does C.4 [Performance of Systems]: Modeling techniques not describe how to model SVA local variable constructs. Apart from the local variable constructs, the most direct General Terms Verification Keywords SVA, Assertion Synthesis influence on the present work is earlier work from [Z] and 181. Our compilation model is similar to on-thefly RCTL model checking work [2]. Our compilation flow is similar to [8]where an extended regular expression language with action statements t o specify state machines, which are synthesized in polynomial time into circuits, however the semantics of Permission to make digital or hard copies of all or pan of this work for pemnnal or elarsmom use is granted without fee provided that copies are PRELIMINARIESnot made or distributed for profit or commencial advantage and that copies Given a set C of an alphabet, C' denotes the set of finite hear this notice and the full citation on the fint page. To copy othenvire, to over C, C" denotes the set of infinite words over C, republish. to post on servers or to distribute to lists. requires prior specific and Em denotes the C* x u , ~h~ length of word permission andlor a fee.

Formal semantics for PSL modeling layer and application to the verification of transactional models

“…Dealing with additional variables is also addressed for instance in [11], [12], but they mainly concentrate on the concept of local variables and the issues related to their semantics in SVA. This context of SVA local variables is considered at the RT level in [11], and the purpose is to generate hardware components for static verification.…”

“…This context of SVA local variables is considered at the RT level in [11], and the purpose is to generate hardware components for static verification. The use of local variables is also addressed in [12].…”

Directed automated symbolic verification of formal properties with local variables

“…Consequently the task of formally verifying properties having SVA local variables is computationally complex, given that the model checking algorithms for linear time logics like SVA are exponential in the length of the property [1]. There exists some literature on using formal methods for checking SVA properties with local variables [4], but given that formal verification does not scale even without local variables, it is unlikely that these methods will scale well in practice.…”