System design methodology of ultraSPARC-I

Yang, Lawrence; Gao, Zhiwei; Mostoufi, J.; Joshi, Raju; Loewenstein, Paul

doi:10.1145/217474.217481

Cited by 25 publications

(9 citation statements)

References 7 publications

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“…For example, verification of the UltraSPARC-I took twice as long as its design [Yan95]. Traditional approaches, such as system emulation and simulation, are becoming increasingly inefficient to address debugging needs.…”

Section: Introductionmentioning

confidence: 99%

Functional debugging of systems-on-chip

Kirovski

Potkonjak

Guerra

1998

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '98

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Due to the exponential growth of both design complexity and the number of gates per pin, functional debugging has emerged as a critical step in the development of a system-on-chip. We introduce a novel debugging approach for programmable systems-on-chip. The new method leverages the advantages of the two complementary functional execution approaches, emulation and simulation. We have developed a set of tools, transparent to both the design and debugging process, which enables the user to run long test sequences in emulation, and upon error detection, roll-back to an arbitrary instance in execution time, and switch over to simulationbased debugging for full design visibility and controllability. The efficacy of the approach is dependent on the method for transferring the computation from one execution domain to another. To enable effective transfer of the computation state, we have identified a set of optimization tasks, established their computation complexity, and developed an efficient suite of optimization algorithms.

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Section: Introductionmentioning

confidence: 99%

Functional debugging of systems-on-chip

Kirovski

Potkonjak

Guerra

1998

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '98

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“…In addition, we need to guarantee the functionality on the target system where the designed chip will work. To reduce the total development time, the chip and its target system should be concurrently developed [1]. To verify the functionality on the target system is an important problem to be solved, but it is quite difficult because only a functional model not adequate for the board-level testing is available at an early design stage.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover it is really difficult to guarantee the correctness of these modeling with a conviction. Some system models have been applied only to limited area such as checking the protocol of a multiprocessor [1]. Thus, we need a verification method that can test the functional design on target systems with directly using all hardware peripherals instead of software peripheral models.…”

Section: Introductionmentioning

confidence: 99%

Virtual chip

Kim

Choi

Lee

et al. 1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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As design complexity increases, functional verification becomes a crucial issue to ensure design correctness at an early design stage. Traditional methods for verifying functional designs are based on the HDL simulation, which is becoming the bottleneck of the design cycle because of the increasing design complexity. The accurate verification ability at the architectural level through a large set of the test programs and real world applications is a foundation for the next design step. In this paper, we describe how to verify a functional model on a real target system. The proposed methodology called virtual chip makes it possible not only to check the functional correctness on real systems, but also to explore design space by measuring the performance effectiveness of various architecture parameters under real applications. Experimental results show that functional models can be verified on real systems using complicated application programs. The proposed functional verification method is faster than HDL simulation and even comparable to emulation.

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“…10 -6. We have extended the Mur~ verification system developed at Stanford with the probabilistic verification scheme. In prior work, the "old" Mur~ system was successfully applied to several industrial protocols [5,6,12,14,17]. We tried the new, probabilistic scheme on some of these protocols.…”

Section: Introductionmentioning

confidence: 99%

Improved probabilistic verification by hash compaction

Stern

Dill

1995

Lecture Notes in Computer Science

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S. We present and analyze a probabilistic method for verification by explicit state enumeration, which improves on the "hashcompact" method of Wolper and Leroy. The hashcompact method maintains a hash table in which compressed values for states instead of full state descriptors are stored. This method saves space but allows a non-zero probability of omitting states during verification, which may cause verification to miss design errors (i.e. verification may produce "false positives"). Our method improves on Wolper and Leroy's by calculating the hash and compressed values independently, and by using a specific hashing scheme that requires a low number of probes in the hash table. The result is a large reduction in the probability of omitting a state. Hence, we can achieve a given upper bound on the probability of omitting a state using fewer bits per compressed state. For example, we can reduce the number of bytes stored for each state from the eight recommended by Wolper and Leroy to only five, and still enumerate state spaces of up to 80 million reachable states while keeping the probability of missing even one state to less than 0.13%. The new verification scheme was tried on some large, industrial examples. The results predicted by the theoretical analysis were confirmed by the outcomes of these examples. We also discuss some practical issues in choosing the number of bits for the compressed state representation, along with some of our experiences in implementing the scheme.

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System design methodology of ultraSPARC-I

Cited by 25 publications

References 7 publications

Functional debugging of systems-on-chip

Functional debugging of systems-on-chip

Virtual chip

Improved probabilistic verification by hash compaction

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