System-in-Package: Electrical and Layout Perspectives

He, Lei; Elassaad, Shauki; Shi, Yiyu; Hu, Yu; Yao, Wei

doi:10.1561/1000000014

Cited by 5 publications

(1 citation statement)

References 84 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Compared with the design complexity and low yield caused by integrating all functions on a single big silicon chip, system-inpackage (SiP) provides a more flexible, efficient, and low-cost development direction that integrates multiple components, such as a CPU, digital logic, analog/mixed signals, memory, sensors, and passive and discrete components, within a single package and a single system. SiP has attracted much research in recent years, which promotes its application in the fields of high-performance computing (HPC), multi-sensor fusion, radio frequency, power electronics, and other fields [1][2][3][4][5]. With the continuous development of integrated circuit technology, electronic products are increasingly developing in the directions of miniaturization, intelligence, high performance, and high reliability.…”

Section: Introductionmentioning

confidence: 99%

Design and Simulation of a System-in-Package Chip for Combined Navigation

Yang,

Shi,

Jin

2024

Micromachines

View full text Add to dashboard Cite

This paper proposes a system-in-package combination navigation chip. We used wire bonding, chip stacking, surface mount, and other processes to integrate satellite navigation chips, inertial navigation chips, microprocessor chips, and separation devices. Finally, we realized the hardware requirements for combined navigation in a 20 mm × 20 mm chip. Further, we performed a multi-physics simulation analysis of the package design. For antenna signals, the insertion loss was greater than −1 dB@1 GHz and the return loss was less than −10 dB@1 GHz. The amplitude of these noises of the signal between the MCU and the IMU was approximately 20%, and the maximum value of the coupling coefficient between signal lines on the top surface was 13.4174%. The ninth mode of the power plane yielded a maximum voltage of 55 mV, and all power delivery networks had a DC voltage drop of less than 2%. The highest temperature in the microsystem was approximately 42 °C. These results show that our design performed well in terms of signal, power, and thermal performance.

show abstract

Section: Introductionmentioning

confidence: 99%

Design and Simulation of a System-in-Package Chip for Combined Navigation

Yang,

Shi,

Jin

2024

Micromachines

View full text Add to dashboard Cite

show abstract

Electrical testing of small-series multi-chip microcircuit samples combining Wire Bond and Flip-Chip technologies

Kirienko

Ershova

Putrolaynen

et al. 2020

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

The paper provides a technical solution and methodology for conducting automated electrical and functional testing of small series samples of multi-chip assemblies. The results of multi-chip assembly samples testing combining Wire Bond and Flip-Chip technologies are presented. Based on the test results, defects that occur during the packaging process are localized and the assembly stages at which these defects occur are determined.

show abstract