System-level communication synthesis and dependability improvements for Network-on-Chip based systems

Abstract

Abstract. Technology scaling into subnanometer range will create process variations that have impact on the overall manufacturing yield and quality. Smaller feature sizes permit to pack more functionality into a single chip. Increasing variability, complexity and communication bandwidth requirements will make the System-on-Chip designer's goal, to design a fault-free system, a very difficult task. Shift from traditional bus-based systems to networked systems solves several design problems but requires more focus on communication modelling. In this work we propose a systemlevel approach for communication modelling and synthesis. It makes possible to calculate precise communication delays that can be taken into account during application scheduling to avoid network congestions. We present a possible application of the proposed framework for scheduling fault-tolerant applications on non-reliable network.

System-level optimization of NoC-based timing sensitive systems

“…In our experiments we are using a dimension-ordered XY routing. Our communication modelling, synthesis and scheduling approach is explained in greater detail in [ 2,3 ].…”

“…The initial schedule is produced by applying a modified list scheduling as described in [ 2,3 ]. List scheduling is a greedy heuristics using a priority list and precedence constraints to schedule the tasks and to minimize the schedule length.…”