System-Level Effects of Soft Errors in Uncore Components

Cho, Hyungmin; Cheng, Eric; Shepherd, Thomas; Cher, Chen-Yong; Mitra, Subhasish

doi:10.1109/tcad.2017.2651824

Cited by 14 publications

(3 citation statements)

References 71 publications

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“…In addition to errors impacting processor cores, it is equally important to consider the impact of errors in uncore components, such as cache, memory, and I/O controllers, as well. In SoCs, uncore components are comparable to processor cores in terms of overall chip area and power [33], and can have significant impact on the overall system reliability [8].…”

Section: Fast Fault Injection In Uncore Componentsmentioning

confidence: 99%

“…Mixed-mode simulation platforms are effective for studying the system-level impact and behavior of soft errors in uncore components as well. As presented in [8], such a platform would achieve a 20,000× speedup over RTL-only injection while ensuring accurate modeling of soft errors. Full-length applications benchmarks can be analyzed by simulating processor cores and uncore components using an instruction-set simulator in an accelerated mode.…”

Section: Fast Fault Injection In Uncore Componentsmentioning

confidence: 99%

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Cross-Layer Resilience Against Soft Errors: Key Insights

Mueller-Gritschneder

Cheng

Sharif

et al. 2020

Dependable Embedded Systems

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Driven by technology scaling, integrated systems become more susceptible to various causes of random hardware faults such as radiation-induced soft errors. Such soft errors may cause malfunction of the system due to corruption of data or control flow, which may lead to unacceptable risks for life or property in safety-critical applications. Hence, safety-critical systems deploy protection techniques such as hardening and redundancy at different layers of the system stack (circuit, logic, architecture, OS/schedule, compiler, software, algorithm) to improve resiliency against soft errors. Here, cross-layer resilience techniques aim at finding lower cost solutions by providing accurate estimation of soft error resilience combined with a systematic exploration of protection techniques that work collaboratively across the system stack. This chapter demonstrates how to apply the cross-layer resilience principle on custom processors, fixed-hardware processors, accelerators, and SRAM memories (with a focus on soft errors) and presents key insights obtained.

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Section: Fast Fault Injection In Uncore Componentsmentioning

confidence: 99%

Section: Fast Fault Injection In Uncore Componentsmentioning

confidence: 99%

Cross-Layer Resilience Against Soft Errors: Key Insights

Mueller-Gritschneder

Cheng

Sharif

et al. 2020

Dependable Embedded Systems

Self Cite

View full text Add to dashboard Cite

show abstract

“…Alleviating the required effort for fault injection runs is crucial when exploring a large design space to find costeffective error resilience solutions. Many approaches have been developed for efficient fault injections, such as reducing the fault injection sites [16] or simulation scale [17], [18]. GangES proposed a mechanism to reduce the overall simulation time by early terminating unnecessary simulations [19].…”

Section: Introductionmentioning

confidence: 99%

Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets

Cho

Kwon

2019

IEEE Access

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Transient errors induced by radiations cause bit-flips in flip-flops (flip-flop soft errors).Modeling the error resilience level of a target system for flip-flop soft errors is a crucial step to achieve a costeffective error resilience solution. This step often requires a significant amount of time and effort for a large number of fault injection simulations. As technology scales, the required effort grows in a new dimension with the increased probability of multi-bit upsets (MBUs). In this work, we present a new estimation model that predicts the resulting error resilience levels for the flip-flop MBU cases. This estimation model only requires the measured soft error effects of the single-bit upset (SBU) cases. This model uses two strategies to address how multiple bit-flips that happen simultaneously in a system affects the outcome of application execution. We evaluate the accuracy level of the MBU estimation model using actual fault injection results on two different processor cores. The two main strategies in our estimation model improve the accuracy levels by more than 7×.

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