System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs

Kumar, Sumeet; Aggarwal, Arnica; Jagtap, Radhika; Zjajo, Amir; Leuken, René van

doi:10.1109/tvlsi.2013.2273003

Cited by 7 publications

(2 citation statements)

References 32 publications

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“…Voltage-Frequency Island (VFI)-based power management is a well-known mechanism to lower the overall energy consumption of a manycore chip within a given performance constraint (Ogras et al 2009; Jang and Pan 2011). Hence, it has been employed to handle the thermal hotspots of conventional 2D as well as 3D manycore chips (Kumar et al 2014a).…”

Section: Performance and Thermal-efficient 3d Noc Incorporating Vfimentioning

confidence: 99%

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Das

Doppa

Pande

et al. 2018

ACM Trans. Des. Autom. Electron. Syst.

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Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal tradeoffs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.

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Section: Performance and Thermal-efficient 3d Noc Incorporating Vfimentioning

confidence: 99%

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Das

Doppa

Pande

et al. 2018

ACM Trans. Des. Autom. Electron. Syst.

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“…The design of the Through Silicon Via (TSV) based vertical interconnect significantly influences thermal conductivity, and thereby impacts system performance, as we previously showed in [7]. However, in addition to TSVs, the composition and depth of die stacks, die thickness, location of power dissipating elements, and stack power density also form critical design parameters that influence thermal behaviour.…”

Section: Introductionmentioning

confidence: 99%

Physical characterization of steady-state temperature profiles in three-dimensional integrated circuits

Kumar

Zjajo

Leuken

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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The thermal performance of three-dimensional integrated circuits is influenced by a number of design and technology parameters. However, the relationship between these parameters and thermal behaviour of die stacks is complex and not well understood. In this paper, we perform a detailed evaluation of the influence of stack composition and depth, thickness of dies, physical location of power dissipating elements and stack power density on steady-state temperature profiles. We examine how each of these parameters affects heat spread within 3D ICs, and highlight the causes for hotspot formation. The results of our analysis illustrate the implications of effective thermal conductivity on temperature sensing zones on dies, and the significant impact of stack power density on overall operating temperature.

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Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture

Das

Pande

2019

Integration

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System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs

Cited by 7 publications

References 32 publications

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Physical characterization of steady-state temperature profiles in three-dimensional integrated circuits

Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture

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