System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip

Abstract

In modern system-on-chip architectures, specialized accelerators are increasingly used to improve performance and energy efficiency. The growing complexity of these systems requires the use of system-level design methodologies featuring high-level synthesis (HLS) for generating these components efficiently. Existing HLS tools, however, have limited support for the system-level optimization of memory elements, which typically occupy most of the accelerator area. We present a complete methodology for designing the private local memories (PLMs) of multiple accelerators. Based on the memory requirements of each accelerator, our methodology automatically determines an areaefficient architecture for the PLMs to guarantee performance and reduce the memory cost based on technology-related information. We implemented a prototype tool, called MNEMOSYNE, that embodies our methodology within a commercial HLS flow. We designed 13 complex accelerators for selected applications from two recently-released benchmark suites (PERFECT and CORTEXSUITE). With our approach we are able to reduce the memory cost of single accelerators by up to 45%. Moreover, when reusing memory IPs across accelerators, we achieve area savings that range between 17% and 55% compared to the case where the PLMs are designed separately. Index Terms-Hardware accelerator, high-level synthesis (HLS), memory design, multibank architecture. I. INTRODUCTION S YSTEM-ON-CHIP (SoC) architectures increasingly feature hardware accelerators to achieve energy-efficient high performance [1]. Complex applications leverage these specialized components to improve the execution of selected computational kernels [2], [3]. For example, hardware accelerators for machine learning applications are increasingly used to identify underlying relations in massive unstructured data [4]-[6]. Many of these algorithms first build an internal model by analyzing very large data sets; then, they leverage Manuscript

DarkMem: Fine-grained power management of local memories for accelerators in embedded systems

“…4). We then extended MNEMOSYNE [16], a prototype CAD tool to generate void Store() { int ping = 0; wait(); while(true) { /// perform DMA request /// ... if (ping) DARKMEM_ACTIVATE(ctrl_B0); else DARKMEM_ACTIVATE(ctrl_B1); /// store produced results /// ... if (ping) DARKMEM_IDLE(ctrl_B0); else DARKMEM_IDLE(ctrl_B1); /// notify compute /// ... ping = !ping; } } Fig. 5.…”

“…• the SRAM banks: based on the technology information (e.g., available SRAM sizes, static power, etc. ), we can implement the corresponding array with different dual-rail SRAMs transparently to the accelerator execution [16]; • the scenario memory controller (SMC): based on the values of the configuration registers, the SMC module determines at the beginning of the execution which banks are not necessary and, therefore, they can be power gated for the entire execution of the accelerator (i.e., until it is configured to start a new execution with different parameters); • the operating mode controller (OMC): based on a set of command signals from the accelerator logic, the OMC module determines the SRAM operating modes (i.e., when to apply power gating to the periphery circuitry or also to the memory cells). The results of these two controllers are then combined with OR gates to determine the actual power management for each single bank.…”

Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel

“…For HLS DSE and memory-based optimization, Pilato et al [30] provided a system-level optimization for a memory system in order to automatically generate more efficient architectures by means of their proposed methodology for HLS DSE. Schafer [12] performed a new method to accelerate the HLS DSE by classifying the HLS optimization knobs, and he also performed an HLS resource sharing DSE by fixing the bitwidth of internal variables in [31].…”

Black-Hat High-Level Synthesis: Myth or Reality?

“…HLS can apply transformations to optimize the performance of the resulting IP component. For example, loop unrolling and multi-port memories can be combined to execute more operations in parallel [18]. An example of resulting FSM is shown in Figure 4a, where the loop body is repeated for a particular number of times based on the value of the parameter ntaps.…”