System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips

Joseph, Jan Moritz; Ermel, Dominik; Bamberg, Lennart; Oritz, Alberto Garcia; Pionteck, Thilo

doi:10.1109/iccd46524.2019.00064

Cited by 2 publications

(2 citation statements)

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“…SA is one of the most-used EDA methods. It can be used at many abstraction levels, from gate-level [14] to system-level optimization [15]. A reason therefore lies in SA's compelling performance, as we will show with a comparison against PSO in this work.…”

Section: Related Workmentioning

confidence: 97%

Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

et al. 2020

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Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the cores in the core graph are uniform and therefore iso-area. This changes for Systems-on-Chip because tasks are mapped to specific blocks and not general-purpose cores. Thus, the area of these specific cores is varying. This requires novel mapping methods. In this paper, we propose a an area-aware cost function for simulated annealing; Furthermore, we advocate the use of nonlinear models as the area is nonlinear: A semi-definite program (SDP) can be used as it is sufficiently fast and shows 20% better area than conventional linear models. Our cost function allows for up to 16.4% better area, 2% better communication (bandwidth times hop distance) and 13.8% better total bandwidth in the network in comparison to the standard approach that accounts for both the network communication and uses cores with varying areas as well.

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Section: Related Workmentioning

confidence: 97%

Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

et al. 2020

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“…Maximum delay and maximum number of links are considered as constraints, while authors claim to improve power consumption and area overhead. In [14], authors propose a heuristic to determine the locations of components, routers and vertical links in 3D NoCs, with five design steps. Method is based on separation of intralayer and inter-layer communications.…”

Section: Related Workmentioning

confidence: 99%

Temperature-Aware Core Mapping for Heterogeneous 3D NoC Design Through Constraint Programming

Demiriz

Ahangari

Öztürk

2020

2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)

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In the context of Network-on-Chip (NoC) based Chip Multiprocessor (CMP) design, core mapping for application specific systems is a challenging problem. In such designs, various decisions have to be made that affect performance and power consumption. Moreover, in emerging 3D NoC systems, by intensification of cooling issues, temperature constraints on hot-spots are added, and problem becomes more complicated. In this paper, an earlier Constraint Programming (CP) methodology for heterogeneous 2D NoC design is extended to 3D model, while critical temperature constraints are accounted. In a singlestage, our approach can choose core types from a set of low, medium and high power, and assign them to appropriate places on the mesh which minimizes the overall computation time and communication cost while satisfying the temperature constraints. To achieve our objective, in addition to cores placement problem, tasks should also be scheduled on corresponding cores with matching performance levels to minimize the overall completion time (makespan). Experimental results show that task completion times are more dependent on the mesh structure for our benchmark data. 3D mesh structures may yield shorter task completion times, without compromising thermal constraints. On the other hand, restricting the peak temperature naturally requires the usage of low-performance computing elements which inherently may delay the processing time.

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System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips

Cited by 2 publications

References 10 publications

Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

Temperature-Aware Core Mapping for Heterogeneous 3D NoC Design Through Constraint Programming

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