System-level performance analysis of multiprocessor system-on-chips by combining analytical model and execution time variation

Kim, Sung‐Chan; Ha, Soonhoi

doi:10.1016/j.micpro.2014.02.003

Cited by 3 publications

(2 citation statements)

References 32 publications

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“…If there are still data to communicate between accelerator and DRAM, the proposed algorithm returns to Step 3. Such per-DMA interval performance estimation is based on the schedule-aware performance estimation proposed in [34]. Otherwise, it calculates the total duration by summing the DMA interval durations (Step 6).…”

Section: Performance Estimation Algorithmmentioning

confidence: 99%

System-Level Communication Performance Estimation for DMA-Controlled Accelerators

Kim

Park

2021

IEEE Access

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The performance of a hardware accelerator is often limited by the communication bandwidth between local on-chip memories and DRAM across on-chip bus. In this paper, a system-level performance estimation algorithm is newly proposed for evaluating the communication performance of direct memory access (DMA) controlled accelerators. The proposed algorithm can estimate the communication performance accurately for both DRAM-limited and bus-limited cases. In detail, the communication performance

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Section: Performance Estimation Algorithmmentioning

confidence: 99%

System-Level Communication Performance Estimation for DMA-Controlled Accelerators

Kim

Park

2021

IEEE Access

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“…In [28], the execution time of single tasks is modeled as a function of the variations in memory accesses count and requests rate, but ignoring any other details of its internal behavior, such as conditional constructs correlations. Finally, also stochastic variables have been used in the performance models of both tasks and task graphs.…”

Section: Related Workmentioning

confidence: 99%

Performance Estimation of Task Graphs Based on Path Profiling

Lattuada

Pilato

Ferrandi

2015

Int J Parallel Prog

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Correctly estimating the speed-up of a parallel embedded application is crucial to efficiently compare different parallelization techniques, task graph transformations or mapping and scheduling solutions. Unfortunately, especially in case of control-dominated applications, task correlations may heavily affect the execution time of the solutions and usually this is not properly taken into account during performance analysis. We propose a methodology that combines a single profiling of the initial sequential specification with different decisions in terms of partitioning, mapping, and scheduling in order to better estimate the actual speed-up of these solutions. We validated our approach on a multi-processor simulation platform: experimental results show that our methodology, effectively identifying the correlations among tasks, significantly outperforms existing approaches for speed-up estimation. Indeed, we obtained an absolute error less then 5% in average, even when compiling the code with different optimization levels.

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