System level performance evaluation of three-dimensional integrated circuit

Abstract

Based on a stochastic wire length distributed model, the reduction in the length of interconnects and gate pitch for three-dimensional (3D) integrated circuit is predicted exactly. Using the results of this model, the impact of increasing of the number of active layers on the system performance in term of the product of delay and power dissipation is evaluated. Comparative results with a two-dimensional (2D) integrated circuit show the system performance of 3D circuit with two active layers is improved at least 50% at sacrifice of 10% chip temperature, demonstrating 3D integration advantage in future integrated circuit design.