System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown

Liu, Taizhi; Chen, Chang-Chih; Cha, Soonyoung; Milor, Linda

doi:10.1016/j.microrel.2015.06.008

Cited by 25 publications

(5 citation statements)

References 14 publications

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“…On the other hand, the transistors used for digital temperature sensor must also be taken into account. The total number of transistors occupied varies depending on the number of ring oscillator stages and will affect the total delays produced by the digital temperature sensor [43]. The same applies to the stable counter and total counter modules which are constructed using transistors to become logic gates and flip flops.…”

Section: Methodsmentioning

confidence: 99%

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Jaafar

Soin²,

Hatta³

et al. 2019

IET Computers & Digital Techniques

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Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. A ring oscillator has been widely used as a digital temperature sensor to sense this thermal effect on FPGAs. The delay generated by the ring oscillator will vary depending on the temperature environment due to negative bias temperature instability, hot carrier injection and electromigration. It is therefore critical to adopt an accurate ring oscillator design to effectively measure the delay in FGPAs. In this study, a digital temperature sensor with a stable ring oscillator is proposed. Measurement periods of 512 and 4096 clock cycles have been implemented and the relationship between temperature, delay and total count has been established. The results show that as the temperature increases to 100°C, the delay decreases by 3.99 and 33.98% for 512 and 4096 clock cycles, respectively. It has been found that in order to reduce the degradation effect on the Virtex-6 FPGA, adopting a measurement period of 512 clock cycles is the best method. The measured data is successfully validated through a set of simulations. Thus, it may benefit a system designer and industrial player, especially in designing temperature-based FPGAs.

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Section: Methodsmentioning

confidence: 99%

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Jaafar

Soin²,

Hatta³

et al. 2019

IET Computers & Digital Techniques

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“…Estimating the impact of degradations on circuits' delay: To translate how a degradation (e.g., an increase in V th or a reduction in V dd ) results in a delay increase in circuits, [17] employed a machine learning scheme after converting the CP into timing graph to estimate delay increases. Looking at a specific path is insufficient to capture how degradation affects the delay because different paths may switch their role w.r.t criticality when degradations come into play [12] -this hold even more when analyzing complex circuits like full processors.…”

Section: Related Workmentioning

confidence: 99%

Modeling the Interdependences Between Voltage Fluctuation and BTI Aging

Salamin

Santen

Amrouch

et al. 2019

IEEE Trans. VLSI Syst.

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With technology scaling the susceptibility of circuits to different reliability degradations is steadily increasing. Aging in transistors due to Bias Temperature Instability (BTI) and voltage fluctuation in the power delivery network of circuits due to IR-drops are the most prominent. In this work, we are reporting for the first time, that there are interdependencies between voltage fluctuation and BTI aging, that are non-negligible. Modeling and investigating the joint impact of voltage fluctuation and BTI aging on the delay of circuits, while remaining compatible with the existing standard design flow, is indispensable in order to answer the vital question, "What is an efficient (i.e. small, yet sufficient) timing guardband to sustain the reliability of circuit for the projected lifetime?" This is, concisely, the key goal of this paper. Achieving that would not be possible without employing a physics-based BTI model that precisely describes the underlying generation and recovery mechanisms of defects under arbitrary stress waveforms. For this purpose, our model is validated against varied semiconductor measurements covering a wide range of voltage, temperature, frequency and duty cycle conditions.To bring reliability awareness to existing EDA tool flows, we create standard cell libraries that contain the delay information of cells under the joint impact of aging and IR-drop. Our libraries can be directly deployed within the standard design flow because they are compatible with existing commercial tools (e.g., Synopsys and Cadence). Hence, designers can leverage the mature algorithms of these tools to accurately estimate the required timing guardbands for any circuit despite its complexity. Our investigation demonstrates that considering aging and IRdrop effects independently, as done in state of the art, leads to employing insufficient and thus unreliable guardbands because of the non-negligible (on average 15% and up to 25%) underestimations. Importantly, considering interdependencies between aging and IR-drop does not only allow correct guardband estimations but it also results in employing more efficient guardbands.

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“…For the effect of TDDB, we need to include two additional parameters for each transistor within a gate, namely, R G2S (gate-to-source resistance), and R G2D (gate-to-drain resistance), because the gate-oxide breakdown paths can happen from gate-to-drain or from gate-to-source [19][20][21][22]. In , plus six global parameters ( ∆ VDD , ∆ T , R pi , C pi1 , C pi2 , Slope ), resulting in a total of (4*N + 6) parameters for each cell.…”

Section: High-dimensional Parameter Space In Aging-aware Standard Celmentioning

confidence: 99%

Multivariate Adaptive Regression Splines in Standard Cell Characterization for Nanometer Technology in Semiconductor

Liu¹

2018

Topics in Splines and Applications

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Multivariate adaptive regression splines (MARSP) is a nonparametric regression method. It is an adaptive procedure which does not have any predetermined regression model. With that said, the model structure of MARSP is constructed dynamically and adaptively according to the information derived from the data. Because of its ability to capture essential nonlinearities and interactions, MARSP is considered as a great fit for high-dimension problems. This chapter gives an application of MARSP in semiconductor field, more specifically, in standard cell characterization. The objective of standard cell characterization is to create a set of high-quality models of a standard cell library that accurately and efficiently capture cell behaviors. In this chapter, the MARSP method is employed to characterize the gate delay as a function of many parameters including process-voltagetemperature parameters. Due to its ability of capturing essential nonlinearities and interactions, MARSP method helps to achieve significant accuracy improvement.

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System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown

Cited by 25 publications

References 14 publications

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Modeling the Interdependences Between Voltage Fluctuation and BTI Aging

Multivariate Adaptive Regression Splines in Standard Cell Characterization for Nanometer Technology in Semiconductor

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