System/Network-On-Chip Test Architectures

Liu, Chunsheng; Chakrabarty, Krishnendu; Jone, Wen-Ben

doi:10.1016/b978-012373973-5.50009-7

Cited by 3 publications

(1 citation statement)

References 91 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Short design cycle times are achieved by integrating a number of predesigned and preverified embedded cores into an SoC. While the testing of such core-based SoCs continues to be a major concern in the semiconductor industry [1], [2], a number of efficient solutions have recently been proposed for test-access mechanism (TAM) optimization and test scheduling [3]- [10]. The design of efficient TAM architectures and SoC test schedules are important problems that need to be addressed during system integration.…”

Section: Introductionmentioning

confidence: 99%

Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs

Bahukudumbi

Chakrabarty

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

Abstract-Wafer-level testing (wafer sort) is used in the semiconductor industry to reduce packaging and test cost. However, a large number of wafer-probe contacts lead to higher yield loss. Therefore, it is desirable that the number of chip pins contacted by tester channels during wafer sort be kept small to reduce the yield loss resulting from improper contacts. Since test time and the number of contacted chip pins are major practical constraints for wafer sort, not all scan-based digital tests can be applied to the die under test. We propose an optimization framework based on mathematical programming (integer linear programming, nonlinear programming, and geometric programming) and fast heuristic methods. This framework addresses test-access mechanism (TAM) optimization and test-length selection for wafer-level testing of core-based digital system-on-chips (SoCs). The objective here is to design a TAM architecture and determine test lengths for the embedded cores such that the overall SoC defect-screening probability at wafer sort is maximized. Defect probabilities for the embedded cores, obtained using statistical yield modeling, are incorporated in the optimization framework. Simulation results are presented for five of the ITC'02 SoC Test benchmarks.

show abstract

Section: Introductionmentioning

confidence: 99%

Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs

Bahukudumbi

Chakrabarty

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

Turbo1500: Core-Based Design for Test and Diagnosis

Wang

Apte

et al. 2009

IEEE Des. Test. Comput.

View full text Add to dashboard Cite

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard

Wang

Apte

et al. 2008

2008 IEEE International Test Conference

View full text Add to dashboard Cite

This paper describes a core-based test and diagnosis integration and automation system, called Turbo1500, which automatically synthesizes test and diagnosis logic in accordance with the IEEE 1500 standard. Turbo1500 serves two major purposes. One is for use as a core test automation tool in a system-on-chip (SOC) environment to automatically connect multiple cores from various sources and create testbenches each targeting an individual core under the control of a chip-level test access port (TAP) controller. The other is for hierarchical (block-by-block) core test and diagnosis when chips on a printed-circuit board are embedded with 1149.1 boundary scan I/O cells and cores under test and diagnosis are surrounded with 1500-compliant wrapper cells. Application experienceshowed that the simplicity of the IEEE 1500 standard combined with an easy-to-use automation tool can make core-based design for test and diagnosis no longer a nightmare, especially when some cores are extremely large or complex.

show abstract

System/Network-On-Chip Test Architectures

Cited by 3 publications

References 91 publications

Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs

Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs

Turbo1500: Core-Based Design for Test and Diagnosis

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard

Contact Info

Product

Resources

About