2006
DOI: 10.1007/11802167_41
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System Software for Flash Memory: A Survey

Abstract: Abstract. Recently, flash memory is widely adopted in embedded applications since it has several strong points: non-volatility, fast access speed, shock resistance, and low power consumption. However, due to its hardware characteristic, namely "erase before write", it requires a software layer called FTL (Flash Translation Layer). This paper surveys the state-of-the-art FTL software for flash memory. This paper also describes problem definitions, several algorithms proposed to solve them, and related research … Show more

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Cited by 91 publications
(48 citation statements)
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“…In order to maintain a small mapping table while achieving reasonable write performance, many FTLs [12,22,26,30] adopt a large mapping granularity (e.g. a block) and use one or multiple log blocks to hold data for incoming writes.…”
Section: Would Increasing Workload Randomness Degrade Performance?mentioning
confidence: 99%
“…In order to maintain a small mapping table while achieving reasonable write performance, many FTLs [12,22,26,30] adopt a large mapping granularity (e.g. a block) and use one or multiple log blocks to hold data for incoming writes.…”
Section: Would Increasing Workload Randomness Degrade Performance?mentioning
confidence: 99%
“…FTLs can be implemented at different granularities in terms of the size of a single entry capturing and address space in the mapping table. Many FTL schemes [8], [24], [19], [25] and their improvement by write-buffering [20] have been studied. A recent page-based FTL scheme called DFTL [11] utilizes temporal locality in workloads to overcome the shortcomings of the regular page-based scheme by storing only a subset of mappings (those likely to be accessed) on the limited SRAM and storing the remainder on the flash device itself.…”
Section: Introductionmentioning
confidence: 99%
“…There has been a host of techniques on improving the performance of the flash translation layer (FTL), which is the part of the flash controller that provides logical-to-physical address mapping, power-off recovery, and wear-leveling. Researchers have studied the FTL algorithms [3] and proposed various improvements on their performance based on block-level associativity [15], onchip caching [1], page-level lazy updates [18], or wear-leveling [11]. On the software side, research has focused on flash-specific bufferpool management schemes [14,16,20,21], query evaluation techniques [7,19,23], and logging [8].…”
Section: Related Workmentioning
confidence: 99%