System Verification of Hardware Optimization Based on Edge Detection

Niu, Xinwei; Fan, Jeffrey

doi:10.4236/cs.2013.43040

Cited by 2 publications

(1 citation statement)

References 4 publications

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“…The Sobel operation is separated into two parts, one part is a Sobel core, and the other part is the Sobel full scan. The Sobel core is a single calculation of the matrix, and the Sobel full scan is used to scan the full image frame [120]. The Sobel operator design is optimized for the hardware implementation of following aspects:…”

Section: Sobel Operator Designmentioning

confidence: 99%

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

Niu¹

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Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools.Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. viiThe contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods -central bus design and coprocessor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced.Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs.Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption. viii MotivationSince the invention of modern computers from the middle of the twentieth century, semiconductor manufacturers have focused mainly on processing as much information as possible while maintaining or minimizing the execution time. In addition, as technology evolves, the size of the tran...

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Section: Sobel Operator Designmentioning

confidence: 99%

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

Niu¹

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To the method of calculation of the main characteristics of promising booster electric pump units of liquid processor engines

Dubynin,

Tolstopyatov,

Zuev

et al. 2023

Siberian Aerospace Journal

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The increase in the capacity of electric power sources, the use of electric motors in the systems for supplying rocket fuel components from foreign companies, the limitations on the power of classical fuel supply systems all these conditions set a trend for studying the possibility of introducing electric drives for rocket engine power systems. The study is devoted to the analysis of the possibility of using electric motors as a drive for the main and auxiliary pumps of liquid rocket engines. Promising developments in the field of rechargeable batteries give grounds for a mathematical justification for the use of this technical solution in order to modernize power systems, both existing rocket engines and samples under development. The article presents a selection of patents for modern technologies for creating high-capacity batteries, an analysis of the use of technology for the use of electric motors in the international market for delivering payloads to orbits, and a rationale for the prospects of this direction in the development of rocket engines. The statistics of the causes of failures of upper stages and their correlation with units, which can be replaced by more reliable systems using electric motors, have been studied. The advantages and disadvantages of power supply systems with the use of electric drives are determined. This study allows us to conclude that the use of electric motors in rocket engine power systems is a promising solution that improves the efficiency of the propulsion system, performance and reliability.

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System Verification of Hardware Optimization Based on Edge Detection

Cited by 2 publications

References 4 publications

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

To the method of calculation of the main characteristics of promising booster electric pump units of liquid processor engines

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