Systematic configuration and automatic tuning of neuromorphic systems

Abstract

Abstract-In the past recent years several research groups have proposed neuromorphic Very Large Scale Integration (VLSI) devices that implement event-based sensors or biophysically realistic networks of spiking neurons. It has been argued that these devices can be used to build event-based systems, for solving real-world applications in real-time, with efficiencies and robustness that cannot be achieved with conventional computing technologies.In order to implement complex event-based neuromorphic systems it is necessary to interface the neuromorphic VLSI sensors and devices among each other, to robotic platforms, and to workstations (e.g. for data-logging and analysis). This apparently simple goal requires painstaking work that spans multiple levels of complexity and disciplines: from the custom layout of microelectronic circuits and asynchronous printed circuit boards, to the development of object oriented classes and methods in software; from electrical engineering and physics for analog/digital circuit design to neuroscience and computer science for neural computation and spike-based learning methods.Within this context, we present a framework we developed to simplify the configuration of multi-chip neuromorphic VLSI systems, and automate the mapping of neural network model parameters to neuromorphic circuit bias values. I. INTRODUCTIONWhile computational neuroscience models simulate neurons and synapses using parameters directly related to their biological characteristics (such as leak conductance, time constants, etc.), neuromorphic VLSI systems emulate them using circuits that can be configured by setting bias voltages and currents. The biases in these circuits are often only indirectly related to the parameters of computational neuroscience models. More generally, the relationship between parameters in theoretical models, software simulations, and hardware emulations of spiking neural networks is highly non-linear, and no systematic methodology exists for establishing it automatically.Current automated methods for mapping the VLSI circuits bias voltages to neural network type parameters are based on heuristics and result in ad-hoc custom made calibration routines. For example, in [1] the authors perform an exhaustive search of the parameter space to calibrate their hardware neural networks, using the simulator-independent description language "PyNN" [2]. This type of brute-force approach is possible because of the accelerated nature of the hardware used, but it becomes intractable for real-time hardware or for very large systems, due to the massive amount of data that must be measured and analyzed to carry out the calibration procedure. An alternative model-based approach is proposed in [3], where the authors fit data from experimental measurements with equations from transistors, circuit models,

Neuromorphic Electronic Circuits for Building Autonomous Cognitive Systems

“…In order to promptly explore the computational properties of different types of large-scale multi-chip computational architectures, it is important to develop a dedicated HW and SW infrastructure, which allows a convenient, user-friendly way to define, configure, and control in real-time the properties of the HW [123], [124] spiking neural networks, as well as a way to monitor in real-time their spiking and non-spiking activity.…”

“…It constitutes a bridge between applications using abstract resources (i.e., neurons and synapses) and the actual processing done at the hardware level through the management of the system's resources, much like a kernel in modern computers [130], and it is compatible with most existing software. The HW and SW infrastructure can be complemented with tools for dynamic parameter estimation methods [131], [132] as well as automated methods for measuring and setting circuitlevel parameters using arbitrary cost-functions at the network level [124].…”

Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System

“…The first problem, that of developing real-time interfaces between the different AER chips to create complex multi-chip systems, is currently being addressed by developing both custom real-time hardware solutions (Gomez-Rodriguez et al, 2006; Fasnacht et al, 2008; Hofstaetter et al, 2010; Jin et al, 2010; Fasnacht and Indiveri, 2011; Scholze et al, 2011), as well as software solutions, and principled systematic methods for configuring network structures and system parameters (Davison et al, 2008; Neftci et al, 2011, 2012; Sheik et al, 2011). …”

STICK: Spike Time Interval Computational Kernel, a Framework for General Purpose Computation Using Neurons, Precise Timing, Delays, and Synchrony

“…Analog design is known to be a difficult endeavour, moreover we would need to robustify the framework to overcome mismatch. Several options are possible, the most straightforward is to use regularization techniques such as the one introduced in (Benosman et al , 2014) or simply using calibration techniques to provide a precisely timed output from analog chip similar to what has been introduced in (Sheik et al , 2012(Sheik et al , , 2011.…”