Systematic defect screening in controlled experiments using volume diagnosis

Seshadri, B.; Gupta, Pallav; Lin, Yi; Cory, Bruce

doi:10.1109/test.2012.6401546

Cited by 6 publications

(3 citation statements)

References 11 publications

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“…Specifically, certain layout features are more difficult to manufacture than others and are more likely to lead to circuit failures. When such features are present multiple times in a chip, they can result in repeated or systematic defects, which can impact the yield and defective-parts-per-million (DPPM) significantly [5,17,18,32,33,38]. Due to modeling errors and algorithmic inaccuracies in removing the resulting systematic variations, process-related corrective actions using OPC/RET techniques are not sufficient for acceptable yield and DPPM [3].…”

Section: Introductionmentioning

confidence: 99%

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

Wang

Pomeranz

Reddy

et al. 2019

ACM Trans. Des. Autom. Electron. Syst.

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Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture layout features that are difficult to manufacture correctly. Avoiding such features prevents the occurrence of potential systematic defects. Layout features that result in DFM guideline violations may not be avoided completely due to the design constraints of chip area, performance, and power consumption. A framework for translating DFM guideline violations into potential systematic defects, and faults, was described earlier.In a cell-based design, the translated faults may be internal or external to cells. In this article, we focus on undetectable faults that are external to cells. Using a resynthesis procedure that makes fine changes to the layout while maintaining the design constraints, we target areas of the design where large numbers of external faults related to DFM guideline violations are undetectable. By eliminating the corresponding DFM guideline violations, we ensure that the circuit does not suffer from low-coverage areas that may result in detectable systematic defects escaping detection, but failing the circuit in the field. The layout resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that the improvement in the coverage of potential systematic defects is significant.

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Section: Introductionmentioning

confidence: 99%

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

Wang

Pomeranz

Reddy

et al. 2019

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

“…Volume diagnosis based analysis [37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][58][59][60][61][62][63][64][65][66] can be applied to different stages of yield ramp-up and serves different purposes, such as identification and quantification of an existing critical feature [37-42, 47, 48], identification of an unknown systematic feature [43], [51], [62], validation and calibration of DFM rules [43], [63], defect density and distribution estimation for a random defect [64], and yield monitoring [40], [61]. In this work, these approaches are all referred as diagnosis driven yield analysis (DDYA).…”

Section: Previous Workmentioning

confidence: 99%

“…The root cause information of defects thus obtained can be categorized as following: 1. Feature failure rate (FFR) estimation [37][38][39][40][41][42][43][44][45][46]; 2. Feature/root cause probability [47], [48]; 3.…”

Section: Previous Workmentioning

confidence: 99%