Systematic designs of buffers in macropipelines of systolic arrays

Wah, Benjamin W.; Aboelaze, Mokhtar; Shang, Weijia

doi:10.1016/0743-7315(88)90030-5

Cited by 17 publications

(8 citation statements)

References 4 publications

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“…k is now a valid schedule, as i is not constrained to be 0. This comes directly from the fact that equation (25) has been removed and, therefore, the constraint Xl _<0 is not necessary.…”

Section: Gaussian Elimination and Gauss-jordan Diagonalizationmentioning

confidence: 97%

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The mapping of linear recurrence equations on regular arrays

Quinton

Dongen²

1989

J VLSI Sign Process Syst Sign Image Video Technol

175

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Abstract. The parallelization of many algorithms can be obtained using space-time transformations which are applied on nested do-loops or on recurrence equations. In this paper, we analyze systems of linear recurrence equations, a generalization of uniform recurrence equations. The first part of the paper describes a method for finding automatically whether such a system can be scheduled by an affine timing function, independent of the size parameter of the algorithm. In the second part, we describe a powerful method that makes it possible to transform linear recurrences into uniform recurrence equations. Both parts rely on results on integral convex polyhedra. Our results are illustrated on the Gauss elimination algorithm and on the Gauss-Jordan diagonalization algorithm.

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“…k is now a valid schedule, as i is not constrained to be 0. This comes directly from the fact that equation (25) has been removed and, therefore, the constraint Xl _<0 is not necessary.…”

Section: Gaussian Elimination and Gauss-jordan Diagonalizationmentioning

confidence: 97%

“…Both steps can be uniformized independently with the above uniformization method. Then the two steps can be put together as described in [51 and [25]. By looking at the time cones of the two algorithms, one can compute a re-indexing transformation which gives a maximal global time cone.…”

Section: Multistep Algorithmsmentioning

confidence: 99%

The mapping of linear recurrence equations on regular arrays

Quinton

Dongen²

1989

J VLSI Sign Process Syst Sign Image Video Technol

175

View full text Add to dashboard Cite

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“…Various algorithms for synthesis of DFC's have been studied [2], [3], [10]. In [2], the number of buffers needed for DFC's interfacing systolic arrays is studied.…”

Section: Introductionmentioning

confidence: 99%

“…In [2], the number of buffers needed for DFC's interfacing systolic arrays is studied. In that paper, a framework for the synthesis of DFC's to generate outputs with the desired clock skews between systolic arrays is shown.…”

Section: Introductionmentioning

confidence: 99%

Synthesis of area-efficient and high-throughput rate data format converters

Bae¹,

Prasanna

1998

IEEE Trans. VLSI Syst.

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This paper proposes two design methodologies for synthesis of area-efficient data format converters (DFC's) with high throughput rate. DFC's are grouped into various classes according to the specification of design parameters. The first design methodology is suitable for design of many representative classes of DFC's. The designs using this methodology are based on a two-dimensional (2-D) architecture. They have maximum throughput rate and are area-efficient. Various design examples are shown to demonstrate improved performance, flexibility and usefulness of this design methodology. For several representative problems, the area requirements of our designs are compared against those obtained by earlier design methodologies. For all the problems considered, this methodology leads to compact designs. The second design methodology employs an architecture using dual buffers. The simple and regular architecture using dual buffers leads to area-efficient DFC's. The design procedure using this methodology is simple and can reduce the design effort in many applications.Index Terms-Area efficiency, data format converter, signal and image processing, throughput performance.

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“…This is because the computer science problem terminates after a single execution of the program whereas the DSP program is executed many , times repetitively and is considered non-terminating. Although some work has been carried out to study buffer requirements in systolic arrays [2], no formal approach has been presented to calculate the Manuscript received February 8, 1994; revised March 28, 1994. This work was supported by the office of naval research under contract number N00014-91-J-1008.…”

Section: Introductionmentioning

confidence: 99%

Calculation of minimum number of registers in arbitrary life time chart

Parhi

1994

IEEE Trans. Circuits Syst. II

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This paper presents a general approach to calculate the minimum number of registers in any digital signal processing (DSP) circuit for any arbitrarily specified lie time chart and periodicity of computation. DSP operations are repetitive and periodic in nature. The life time chart specifies the life period of all variables in a single frame and the subsequent frames are computed in a periodic manner. We present the techniques for the calculation of minimum number of registers by using the life t h e chart and the circular life time graph.

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Systematic designs of buffers in macropipelines of systolic arrays

Cited by 17 publications

References 4 publications

The mapping of linear recurrence equations on regular arrays

The mapping of linear recurrence equations on regular arrays

Synthesis of area-efficient and high-throughput rate data format converters

Calculation of minimum number of registers in arbitrary life time chart

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