SystemC/TLM semantics for heterogeneous system-on-chip validation

Maraninchi, Florence; Moy, Matthieu; Cornet, Jérôme; Maillet-Contoz, Laurent; Helmstetter, Claude; Traulsen, Claus

doi:10.1109/newcas.2008.4606376

Cited by 8 publications

(8 citation statements)

References 12 publications

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“…() In general, the goal of the formalization process is to extract a formal model from a SystemC program, so that tools like model checkers can be applied. For example, Zeng et al in Zeng and Zhang translate a subset of the operational semantics of SystemC as a guarded assignment system and use this translated model as an input for symbolic executors and checkers. However, all these formalizations consider semantics of SystemC and its simulator in some form of global model , and they also suffer from the state space explosion when dealing with industrial and large systems.…”

Section: Related Workmentioning

confidence: 99%

“…There has been a lot of work on the formalization of SystemC. [42][43][44][45][46] In general, the goal of the formalization process is to extract a formal model from a SystemC program, so that tools like model checkers can be applied. For example, Zeng et al in Zeng and Zhang 44 translate a subset of the operational semantics of SystemC as a guarded assignment system and use this translated model as an input for symbolic executors and checkers.…”

Section: Related Workmentioning

confidence: 99%

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Formal verification of probabilistic SystemC models with statistical model checking

Ngo

Legay

2017

J Software Evolu Process

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SUMMARYTransaction-level modeling with SystemC has been very successful in describing the behavior of embedded systems by providing high-level executable models, in which many of them have inherent probabilistic behaviors, e.g., random data and unreliable components. It thus is crucial to have both quantitative and qualitative analysis of the probabilities of system properties. Such analysis can be conducted by constructing a formal model of the system under verification and using Probabilistic Model Checking (PMC). However, this method is infeasible for large systems, due to the state space explosion. In this article, we demonstrate the successful use of Statistical Model Checking (SMC) to carry out such analysis directly from large SystemC models and allow designers to express a wide range of useful properties. The first contribution of this work is a framework to verify properties expressed in Bounded Linear Temporal Logic (BLTL) for SystemC models with both timed and probabilistic characteristics. Second, the framework allows users to expose a rich set of user-code primitives as atomic propositions in BLTL. Moreover, users can define their own fine-grained time resolution rather than the boundary of clock cycles in the SystemC simulation. The third contribution is an implementation of a statistical model checker. It contains an automatic monitor generation for producing execution traces of the model-under-verification (MUV), the mechanism for automatically instrumenting the MUV, and the interaction with statistical model checking algorithms.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Formal verification of probabilistic SystemC models with statistical model checking

Ngo

Legay

2017

J Software Evolu Process

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“…There has been a lot of work on the formalization of SystemC [8], [17]. The goal is to extract a formal model from a SystemC program, so that tools like model-checkers can be applied.…”

Section: Related Work and Conclusionmentioning

confidence: 99%

Statistical Model Checking for SystemC Models

Ngo

Legay

Quilbeuf

2016

2016 IEEE 17th International Symposium on High Assurance Systems Engineering (HASE)

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Abstract-Transaction-level modeling with SystemC has been very successful in describing the behavior of embedded systems by providing high-level executable models, in which many of them have an inherent probabilistic behavior, i.e., random data, unreliable components. It is crucial to evaluate the quantitative and qualitative analysis of the probability of the system properties. Such analysis can be conducted by constructing a formal model of the system and using probabilistic model checking. However, this method is infeasible for large and complex systems due to the state space explosion. In this paper, we demonstrate the successful use of statistical model checking to carry out such analysis directly from large SystemC models and allows designers to express a wide range of useful properties.

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“…In [6], the formalization uses timed automata, with a connection to Uppaal [8]. In [13,10] we describe several formalizations and connections to SMV [11], SPIN [7], etc. However, all these formalizations include some form of a global model for the SystemC scheduler, and the TLM principles in SystemC are not formalized, in the sense that there is no clear definition of what a TLM component is.…”

Section: Related Workmentioning

confidence: 99%

Formal and executable contracts for transaction-level modeling in SystemC

Bouhadiba

Maraninchi

Funchal

2009

Proceedings of the Seventh ACM International Conference on Embedded Software

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Transaction-Level Modeling (TLM) for systems-on-a-chip (SoCs) has become a standard in the industry, using SystemC. With SystemC/TLM, it is possible to develop an executable virtual prototype of a hardware platform, so that software developers can start writing code long before the actual chip is available. A hardware model in SystemC/TLM can be very abstract, compared to the detailed RTL model. It is clearly component-based, with guidelines defining how components should be designed for use in any TLM context. However, these guidelines are quite informal for the moment. In this paper, we establish a structural correspondence between functional SystemC/TLM models and a formal component-model for embedded systems called 42, for which we have defined a notion of control contract, and an execution mode for systems made of components' contracts. This is a way of formalizing the principles of functional SystemC/TLM. Moreover, it allows the combined use of SystemC/TLM components with 42 components. Demonstrating that such a combined use is possible is key to the adoption of formal components' definitions in the community of TLM users.

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SystemC/TLM semantics for heterogeneous system-on-chip validation

Cited by 8 publications

References 12 publications

Formal verification of probabilistic SystemC models with statistical model checking

Formal verification of probabilistic SystemC models with statistical model checking

Statistical Model Checking for SystemC Models

Formal and executable contracts for transaction-level modeling in SystemC

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