Systolic architectures for artificial neural nets

Khan, E.; Ling, N.

doi:10.1109/ijcnn.1991.170469

Cited by 17 publications

(2 citation statements)

References 3 publications

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“…The parallel implementation models take advantage of several parallel computational structures inherent in ANNs to achieve high processing rates. As a result, ANNs have been implemented on several commercially available multiprocessor platforms, such as the connection machine (Deprit 1989), MPP (Kosko 1992), and BBN butterfly (Feldman et al 1988), and also on several different architectures, such as systolic arrays (Khan 1991), hyper-cubes , reduced mesh of trees (Luttrell 1989), and SIMD arrays (Shams and Przytula 1991).…”

Section: Introductionmentioning

confidence: 99%

Parallel implementation of multilayered neural networks based on Map-Reduce on cloud computing clusters

Zhang

2015

Soft Comput

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To meet the requirements of big data processing, this paper presents an efficient mapping scheme for a fully connected multilayered neural network, which is trained by using back-propagation (BP) algorithm based on MapReduce of cloud computing clusters. The batch-training (or epoch-training) regimes are used by effective segmentation of samples on the clusters, and are adopted in the separated training method, weight summary to achieve convergence by iterating. For a parallel BP algorithm on the clusters and a serial BP algorithm on an uniprocessor, the required time for implementing the algorithms is derived. The performance parameters, such as speedup, optimal number and minimum of data nodes are evaluated for the parallel BP algorithm on the clusters. Experiment results demonstrate that the proposed parallel BP algorithm in this paper has better speedup, faster convergence rate, less iterations than that of the existed algorithms.

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Section: Introductionmentioning

confidence: 99%

Parallel implementation of multilayered neural networks based on Map-Reduce on cloud computing clusters

Zhang

2015

Soft Comput

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“…Systolic arrays are a class of architecture where the processing elements and the interconnecting scheme can be optimized for solving certain classes of algorithms. Matrix multiplication belongs to this class of algorithms (Leiserson 1982), and it is known that neural network simulation relies heavily on matrix multiplication (Beiu 1989, Kham and Ling 1991, Kung and Hwang 1989b. The SIMD arrays are similar structures, the main difference being that the elementary processing elements have no controllers and that a central controller is in charge of supervising the activity of all the elementary processing elements.…”

Section: E1442 Typical and Recent Examplesmentioning

confidence: 99%

Digital integrated circuit implementations

Beiu¹

Handbook of Neural Computation

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This section considers some of the alternative approaches towards modeling biological functions by digital circuits. It starts by introducing some circuit complexity issues and arguing that there is considerable computational and physiological justification that shallow threshold gate circuits are computationally more efficient than classical Boolean circuits. We comment on the tradeoff between the depth and the size of a threshold gate circuit, and on how design parameters like fan-in, weights and thresholds influence the overall area and time performances of a digital neural chip. This is followed by briefly discussing the constraints imposed by digital technologies and by detailing several possible classification schemes as well as the performance evaluation of such neurochips and neurocomputers. Lastly, we present many typical and recent examples of implementation and mention the 'VLSI-friendly learning algorithms' as a promising direction of research.

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Systolic VLSI and FPGA Realization of Artificial Neural Networks

Meher

2010

Computational Intelligence in Optimization

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Systolic architectures for artificial neural nets

Cited by 17 publications

References 3 publications

Parallel implementation of multilayered neural networks based on Map-Reduce on cloud computing clusters

Parallel implementation of multilayered neural networks based on Map-Reduce on cloud computing clusters

Digital integrated circuit implementations

Systolic VLSI and FPGA Realization of Artificial Neural Networks

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