Systolic array implementations of neural nets on the MasPar MP-1 massively parallel processor

Chinn, G.C.; Grajski, Kamil A.; Chen, C.; Kuszmaul, Christopher L.; Tomboulian, S.

doi:10.1109/ijcnn.1990.137711

Cited by 17 publications

(5 citation statements)

References 7 publications

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“…Early study [5][6] mainly focused on the design of parallel neural network and their implementation. Reference [5] realizes a BP network based on nodes in parallel way, and reference [6] realizes a parallel algorithm of BP network, which has the characteristic of combining training set in parallel way (data in parallel way) and nodes in parallel way.…”

Section: Introductionmentioning

confidence: 99%

“…Reference [5] realizes a BP network based on nodes in parallel way, and reference [6] realizes a parallel algorithm of BP network, which has the characteristic of combining training set in parallel way (data in parallel way) and nodes in parallel way. Both of the papers do not consider the problem of dynamic load balancing of communication.…”

Section: Introductionmentioning

confidence: 99%

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A new parallel back-propagation algorithm for neural networks

Wang

Zhao

et al. 2011

Proceedings of 2011 IEEE International Conference on Grey Systems and Intelligent Services

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The BP neural network is one of the most widely used neural networks. It uses the back-propagation algorithm for training, and the algorithm has the disadvantage of slow convergence and long training time. In this paper, a parallel BP neural network algorithm with a balancing scheme of dynamic load is presented in order to reduce the training time of large scale neural networks. The experimental results indicate that the proposed algorithm has the feature of speeding-up computation for the large scale neural networks.Keywords-BP neural network, parallel algorithm, dynamic load balancing I.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A new parallel back-propagation algorithm for neural networks

Wang

Zhao

et al. 2011

Proceedings of 2011 IEEE International Conference on Grey Systems and Intelligent Services

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“…Two dimensional systolic configurations to implement the backpropagation ANNs have been adopted by the researchers in the past few years [3,5,9,. These attempts exploit the inherent parallelism of ANNs taking advantage of the capability for pipelined execution of the multiple training patterns.…”

Section: Introductionmentioning

confidence: 99%

An efficient approach to mapping large anns onto fixed systolic architectures

Bekakos

Efremides

1998

International Journal of Computer Mathematics

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One of the best solutions to the communication problems arising in artificial neural networks (ANNs), due to the high interconnectivity of neurons, is achleved through their implementation on systolic array architectures (SAAs). The case of systematical mapping policies from ANNs to SAAs, however, is little explored. In this work, an efficient mapping policy is explored, capable of implementing an ANN on the available fixed systolic array, while it still allows the exploitation of the training pattern pipelined parallelism and remains feasible from the aspect of the hardware implementation cost.

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“…At Carnegie Mellon University, the back-propagation learning algorithm has been performed on a systolic array computer [11]. Kung and Hwang proposed several implementations of neural network models on a systolic array [10], which was further mapped onto a parallel SIMD machine (the MasPar Mp-1) in [2]. Steck et al also presented an implementation of the recursive least squares learning algorithm [13] on an Intel iPSC/2, a cubically-connected machine.…”

mentioning

confidence: 99%

Parallel Neural Learning for Control Problems on a Bus-Based Architecture

Hong

Lee²

1999

Int. J. High Speed Comp.

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In [6], we distributed training instances over a single-channel broadcast communication model to speed up execution of the back-propagation learning algorithm for classification problems. In this paper, we extend this concept to control problems, where the output is not necessarily 0 or 1, but ranges over an interval. We first propose a modified back-propagation learning algorithm that incrementally decreases the error threshold by half in order to process training instances with large weight changes as quickly as possible. This modified back-propagation learning algorithm is then parallelized using the single-channel broadcast communication model to n processors, where n is the number of training instances. Finally, the parallel back-propagation learning algorithm is modified for execution on a bounded number of processors to cope with real-world conditions.

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Systolic array implementations of neural nets on the MasPar MP-1 massively parallel processor

Cited by 17 publications

References 7 publications

A new parallel back-propagation algorithm for neural networks

A new parallel back-propagation algorithm for neural networks

An efficient approach to mapping large anns onto fixed systolic architectures

Parallel Neural Learning for Control Problems on a Bus-Based Architecture

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