Systolic FFT Processors: A Personal Perspective

Abstract

This paper provides a personal perspective on developments in the implementation of two systolic fast Fourier transform processors over the last 25 years and identifies some of the lessons learned. This has been a period of tremendous advancements in integrated circuit technology that is demonstrated by the resulting processors. The first processor is the Modular Transform Processor that was developed at TRW in the 1982-1984 time frame using VLSI technology. It is a set of six large circuit boards that computes 4,096-point fast Fourier transforms using 22-bit floating-point arithmetic at sustained data rates of 40 MSPS. The second processor is a single ASIC chip systolic FFT processor developed by the Mayo Foundation in the 2001-2002 time frame that computes 4,096-point FFTs using 16-bit fixed-point arithmetic at sustained data rates of 200 MSPS. Some thoughts on the future directions of systolic FFT processor development are offered. Future systems will compute large transforms (e.g., 16 K-point to 1 M-point) at high data rates (e.g., 500 MSPS to 1 GSPS), will employ more precise arithmetic (e.g., 32-bit single precision IEEE Standard floating-point arithmetic), will consume very low power (e.g., on the order of one watt) and will be realized on a single chip.

Parallel - pipelined radix-2² FFT architecture for real valued signals

“…The first two stages compute only real butterflies. According to the input order of the data, the first butterfly computes the pairs of samples in the following order: (O,8), (2,10), (4,12), (6,14), (1, 9), (3,11), (5,13), (7,15). This circuit first processes the even samples and then the odd samples.…”

“…Much research has been carried out on designing pipelined architectures for computation of FFT of complex valued signals (CFFT) [6] - [9] , but not on RFFT. For the applications with real input signals, a dedicated pipelined RFFT architec ture can lead to savings in power consumption and area.…”

Fully Systolic FFT Architecture for Giga-sample Applications

“…The design presented in [13] implements a 2K/4K/8K multimode FFT and achieves 9 MHz clock frequency, at a computation time of up to 450 μs. Finally, a single ASIC chip, systolic FFT processor, developed by the Mayo Foundation computes 4096-point FFTs sustaining a throughput of 200 Ms/s [26]. Considering FPGA implementations, the corresponding XILINX designs (www.xilinx.com) achieve equal maximum operating frequency of 200 MHz, but occupy considerably larger chip area than the R4 3 approach.…”