T1/E1/J1 receiver in CMOS

Abstract

SUMMARYBehavioural model, simulation and testing results of a mixed-signal short-/long-haul receiver suitable for high-speed T1/E1/J1 application in CMOS are presented. The measured results demonstrate successful recovery of distorted incoming signals attenuated from 0 to 44 dB (max). The mixed-signal part of the receiver chip occupies area of 1.2mm×1.8mm in CMOS 0.35 m process and requires typically 120 mW of power at 3.3 V power supply. Digital framer supports the operation of the receiver whereas local RAM is used for storing the unshielded twisted pair cable models that can be easily reprogrammed.