Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation

Hsiao, Shen-Fu; Wu, Po-Han; Wen, Chia-Sheng; Meher, Pramod Kumar

doi:10.1109/tcsii.2014.2386232

Cited by 19 publications

(33 citation statements)

References 10 publications

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“…Several methods try to overcome this shortcoming with as little extra resources as possible. These methods include the ATA method [4], iATA [5], the bipartite method [6], SBTM [7], STAM [8] and the generalized multipartite method [9], [10], [11]. More details about these methods are presented in Section IV.…”

Section: Classes Of Methods Based On Approachmentioning

confidence: 99%

Flexible Fixed-Point Function Generation for FPGAs

Istoan¹,

Pasca²

2017

2017 IEEE 24th Symposium on Computer Arithmetic (ARITH)

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Implementations of the reciprocal, square root and reciprocal square root often share a common structure. This article is a survey and comparison of methods (with only slight variations for the three cases) for computing these functions. The comparisons are made in the context of the same accuracy target (faithful rounding) and of an arbitrary fixed-point format for the inputs and outputs (precisions of up to 32 bits). Some of the methods discussed might require some form of range reduction, depending on the input's range. The objective of the article is to optimize the use of fixed-size FPGA resources (block multipliers and block RAMs). The discussions and conclusions are based on synthesis results for FPGAs. They try to suggest the best method to compute the previously mentioned fixedpoint functions on a FPGA, given the input precision. This work compares classical methods (direct tabulation, multipartite tables, piecewise polynomials, Taylor-based polynomials, Newton-Raphson iterations). It also studies methods that are novel in this context: the Halley method and, more generally, the Householder method.

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Section: Classes Of Methods Based On Approachmentioning

confidence: 99%

Flexible Fixed-Point Function Generation for FPGAs

Istoan¹,

Pasca²

2017

2017 IEEE 24th Symposium on Computer Arithmetic (ARITH)

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“…Bit heaps are a generalization of the bit arrays classically used in multiplier design [22]. In FloPoCo, they have been used since 2013 [15] to capture summations in a surprisingly large number of operators, including sums of products and more generally polynomials of several variables, but also all sorts of sums of tabulated values, for instance in KCM-based FIR and IIR filters [17] or in multipartite table methods for function evaluation [23]. They are in principle an elegant way of decoupling the description of a problem with the generation of target-optimized hardware (Figure 2).…”

Section: The Bit Heap Grand Planmentioning

confidence: 99%

Reflections on 10 Years of FloPoCo

Dinechin¹

2019

2019 IEEE 26th Symposium on Computer Arithmetic (ARITH)

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“…But TI still takes a significant portion of the total table size, as will be seen in the next section. We can employ the concept of lossless table decomposition method recently proposed in [27] to further reduce the table size of TI.…”

Section: Compression For Table Of Initial Valuesmentioning

confidence: 99%

“…The differences of values are stored in another new table. The above decomposition of TI into and proposed in [27] increases by one the number of operands to be added up in the final multi-operand adder, leading to larger adder area cost.…”

Section: Compression For Table Of Initial Valuesmentioning

confidence: 99%

“…In general LUT-based function evaluation methods can be divided into two categories: piecewise polynomial approximation (PPA) [9], [10], [11], [12], [13], [14], [15], [16], [17] and table-addition (TA) [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], depending on whether multipliers are used or not. The former category partitions the initial input interval into subintervals (segments) and approximate the piecewise function values in each segment by low-order (usually degree-one or degree-two) polynomials whose coefficients or boundary function values are stored in LUT.…”

Section: Introductionmentioning

confidence: 99%

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Hierarchical Multipartite Function Evaluation

Hsiao

Wen

Chen

et al. 2017

IEEE Trans. Comput.

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Function evaluation is an important arithmetic computation in many signal processing applications, such as special function units in modern graphics processing units (GPUs). Hardware implementations of function evaluation usually consists of lookup tables (LUT) and some simple arithmetic units of multipliers and/or adders. LUT usually takes a significant portion of total area cost, especially when function evaluators are allowed to compute several different arithmetic functions with shared arithmetic units where evaluation of each function needs separate LUT. In this paper, we focus on the category of table-addition (TA) function evaluators that are composed of two types of LUT, table of initial values (TI) and table of offset values (TO), followed by a multi-operand adder. It has been shown that multipartite table method (MP) has significant improvement over prior similar designs such as symmetric bipartite table methods (SBTM) and symmetric table addition methods (STAM) for applications with low-to-medium precision requirements. This paper presents an extension of MP, called hierarchical multipartite (HMP), which further reduces total table size by applying several levels of table decompositions. Furthermore, we perform the bit-width optimization by jointly considering the impacts of all error sources during the search of best table decompositions, leading to more efficient hardware design. Besides, a new lossless decomposition of TI is presented, resulting in additional saving of table size without incurring any extra errors. Experimental results show that the proposed design can efficiently reduce the total area cost in ASIC and FPGA implementations.

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Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation

Cited by 19 publications

References 10 publications

Flexible Fixed-Point Function Generation for FPGAs

Flexible Fixed-Point Function Generation for FPGAs

Reflections on 10 Years of FloPoCo

Hierarchical Multipartite Function Evaluation

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