Tailoring IGZO-TFT architecture for capacitorless DRAM, demonstrating > 10³s retention, >10¹¹ cycles endurance and L_g scalability down to 14nm

High-Performance Thin-Film Transistor with Atomic Layer Deposition (ALD)-Derived Indium–Gallium Oxide Channel for Back-End-of-Line Compatible Transistor Applications: Cation Combinatorial Approach

“…56 Since D it was assumed to be zero for N T calculation, extracted N T value can be interpreted to be the maximum trap densities formed in a given system. Although the unannealed In 2 O 3 TFTs had a simple resistor behavior, the TFTs with the In 2(1−x) Ga 2x O y channel layer [x = 0.20, 0.29, and 0.37] exhibited a decent μ FE (15−20 cm 2 /(V s)) and I ON/OFF ratio (>10 7 ). The facile electrical activation of ALD-derived oxide TFTs without any post-deposition annealing is interesting, because the sputtered oxide TFTs require moderate thermal annealing (≥300 °C) to activate the switching transfer characteristics.…”

“…Recently, the supreme properties of O/S have gained tremendous attention as a next-generation channel material in 3D DRAM, NAND, and M3D to meet the never-ending Moore’s law in the intelligent semiconductor chips. − For a semiconductor application, the conventional physical vapor deposition (PVD) process cannot satisfy the stringent requirements such as conformal deposition and accurate thickness controllability on 3D nanoscaled structure, even though most of the work on O/S TFTs, until now, has been focused on the PVD route. − As an alternative approach, the atomic layer deposition (ALD) technique can provide good conformality and accurate control of the composition thickness on the basis of its unique self-limiting growth behavior . These advantages enable the O/S channel layer to be embedded in complex three-dimensional (3D) device structures, such as FinFET, gate-all-around (GAA) transistor, 3D NAND devices, etc.…”

A 3D Vertical-Channel Ferroelectric/Anti-Ferroelectric FET With Indium Oxide

“…Previous works theoretically and experimentally show that shorter gate length (Lg) and thinner channel help to mitigate the weak erase issue by enhancing the electric field in the Fe-HfO2 layer [8][9][10]. For 3D vertical channel FeFETs, OS channel material should be conformally deposited by atomic layer deposition (ALD) in a high-aspect ratio trench structure [11][12][13][14].…”

Roles of Oxygen Interstitial Defects in Atomic-Layer Deposited InGaZnO Thin Films with Controlling the Cationic Compositions and Gate-Stack Processes for the Devices with Subμm Channel Lengths

“…Alternatively, amorphous oxide semiconductors (AOS) have been considered as one of the most promising channel materials for the BEOL transistors and monolithic 3D integration in future logic and memory applications such as capacitor-less DRAM due to their largearea uniformity, competitive carrier mobility, and ultralow leakage current components. 6,7 From these technical backgrounds, the introduction of AOS channel thin film transistor (TFT) has been pursued to reduce the cell footprint and open the possibility of stacking individual cells. 8−11 For developing and characterizing the devices with nanoscale AOS channels, the device feasibility should be urgently explored for potential implementation of highly scaled devices in future logic and memory applications.…”

“…As an example, polycrystalline silicon (poly-Si) channel has been widely used for vertical-NAND flash memory and back-end-of-line (BEOL) transistors. , However, poly-Si channels suffer from critical limitations for further device scaling due to the degradation in carrier mobility and the poor uniformity in device characteristics caused by grain-boundary effects. − Furthermore, the 3D integration and cell size reduction, which correspond to the ultimate path toward higher-density DRAM, is now facing such problems as an implementation of highly scaled storage capacitor. Alternatively, amorphous oxide semiconductors (AOS) have been considered as one of the most promising channel materials for the BEOL transistors and monolithic 3D integration in future logic and memory applications such as capacitor-less DRAM due to their large-area uniformity, competitive carrier mobility, and ultralow leakage current components. , …”