Tailoring Oxide/Silicon Carbide Interfaces: NO Annealing and Beyond

Rozen, John

doi:10.5772/54396

Cited by 9 publications

(5 citation statements)

References 139 publications

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“…The difference in V FB between ideal CV curve and HFCV curve corresponds to an effective positive oxide charge of 1.94×10 11 cm -2 . The HFCV curve of MOSCAP2 was shifted further to the left as compared to HFCV curve of MOSCAP1 and the extracted V FB was -0.346V, corresponding to an effective positive oxide charge of 2.91×10 11 cm -2 .The post oxidation annealing with N 2 O or NO is known to introduce fixed oxide charge into the gate oxide of 4H-SiC [5]. The difference in V FB of MOSCAP2 and MOSCAP1 suggested that the level of fixed oxide charge is also sensitive to the processing history, where either the pre-oxide process (high temperature implantation and activation) or the post-oxide process (rapid thermal annealing at 1000 o C to form source/drain Ohmic contact in MOSFETs) might have introduced additional positive fixed oxide charges into the gate oxide.…”

Section: Resultsmentioning

confidence: 98%

Negative Bias Temperature Instability of SiC MOSFET

Yen

Hung

et al. 2016

MSF

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MOSFETs and MOS capacitors (MOSCAPs) have been fabricated on Si-face of 4H-SiC to investigate the negative bias temperature instability (NBTI) characteristics of SiC MOSFETs. The shifts of threshold voltage of MOSFETs ranged from -216mV to -1257mV after stressed by 1000sec of -1V to -15V gate bias, correspondingly. The negative shift of the threshold voltage indicated that there were positive charges piled up at or near the oxide/SiC interface. In the mean time, the flat-band voltage shifts of SiC MOSCAPs using the same oxide after stressed by -15V bias for 28800 sec at 175°C were negligible, due to insufficient supply of holes, thus suggesting that the NBTI observed in this study was primarily participated by hole trapping, instead of electron emission. The time evolution of DVth induced by negative bias stress was found to saturate quickly, also suggesting that positive charges were primarily coming from trapping of pre-existing near-interface oxide traps, instead of generation of interface traps. The DVth induced by negative bias stress was lower at higher temperature which might be attributed to faster recovery of hole trapping at elevated temperature.

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Section: Resultsmentioning

confidence: 98%

Negative Bias Temperature Instability of SiC MOSFET

Yen

Hung

et al. 2016

MSF

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“…For instance, oxynitridation processes using NO and N2O provide an effective technique for reducing Dit in SiO2/4H-SiC near the conduction band and increasing the channel mobility. [1][2][3] This work is focused on the investigation of the effect of post oxidation annealing (POA) processes carried out after the deposition of high-temperature oxide (HTO) layer used for dielectric gate formation.…”

Section: Introductionmentioning

confidence: 99%

Study of the Post-Oxidation-Annealing (POA) Process on Deposited High-Temperature Oxide (HTO) Layers as Gate Dielectric in SiC MOSFET

Severino

Piluso

Stefano

et al. 2019

MSF

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In the development of SiC MOSFETs, further improvements are ongoing to improve device performances. One of the critical part at the device level is the gate oxide/semiconductor interface, being the gate oxide a standard SiO2 layer. This work is focused on the investigation of the effect of post oxidation annealing process (POA) carried out after the deposition of high-temperature oxide (HTO) layer used for dielectric gate formation by using NO and N2O gasses. The variation of Dit by applying the POA in N2O is considerable with respect to the as-deposited oxide layer as the density is reduced of about two order of magnitude. A further reduction of interface trap density from 2.3×1010 to 8.5×109 traps/cm2 has been observed when NO POA process was applied. Full vertical power MOSFETs were also analyzed in order to measure the channel mobility of the device. Channel mobility has been seen to raise its value from 45 cm2/Vs to a value of about 62 cm2/Vs when NO-based POA process was performed. NO-based POA process results in a much more effective interface at device level.

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“…SiC is also the only wide band semiconductor material being able to form thermally grown oxide, but the thermal oxidation of SiC usually creates a high level of density of interface states (D it ) which resulted in extremely low channel mobility as compared to Si and prevented the realization of the full potential of SiC. Several kinds of passivation techniques including post-oxidation annealing by NO, N 2 O or POCl 3 [1] have been proposed to improve the D it and mobility of SiC. However, issues such as threshold voltage instability [2] remained with these passivation techniques, which need to be addressed to further improve the performance and reliability of SiC MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Negative Bias Temperature Instability on Subthreshold Swing of SiC MOSFET

Yen¹,

Hung²,

Hung³

et al. 2017

MSF

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The NBTI characteristics of SiC MOSFET were studied by the subthreshold swing. The subthreshold swing was found to be very sensitive to the starting bias of transfer curve. The increase of subthreshold swing for MOSFET with poor oxide reached 400% when the starting bias was-15V. The increase of subthreshold swing was caused by enhanced hole trapping which could be explained by the mechanism of positively charged interface states assisted hole trapping. The increase of subthreshold swing for MOSFET with improved gate oxide was reduced to about 40% when the starting bias was-20V and the value approached saturation for starting biases more negative than-10V, which can also be explained by the proposed mechanism. The increase of subthreshold swing for MOSFET with improved oxide was not sensitive to the temperature. The increase of subthreshold swing at 175°C was only 5%~7% higher than that at room temperature.

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Tailoring Oxide/Silicon Carbide Interfaces: NO Annealing and Beyond

Cited by 9 publications

References 139 publications

Negative Bias Temperature Instability of SiC MOSFET

Negative Bias Temperature Instability of SiC MOSFET

Study of the Post-Oxidation-Annealing (POA) Process on Deposited High-Temperature Oxide (HTO) Layers as Gate Dielectric in SiC MOSFET

Negative Bias Temperature Instability on Subthreshold Swing of SiC MOSFET

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