Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs

Abstract

This paper describes the implementation of a sigma-delta ( ) A/D converter within an FPGA, with minimal use of external analog components. The approach takes advantage of existing low-voltage differential signaling (LVDS) I/O pads; this allows the implementation of lowcost ADCs into existent FPGAs, even though such digital devices do not posses analog interfacing capabilities at first. The converter was implemented in an actual FPGA and had its performance evaluated.

Enhanced software defined meter for smart utility networks

“…In a different implementation, the nominal resolution has been increased to 12 bit, cascading a 4 th -order CIC and a 127-coefficient FIR filter (similarly to what proposed in [36]); in this case, the overall decimation factor is 2 10 .…”

Design development & performance analysis of high speed comparator for reconfigurable ΣΔ ADC with 180 nm TSMC technology

“…• Passive analog RC integrator • FPGA/ASIC differential pin as Comparator • Edge trigged DFF and buffer • Digital processing blocks The work contributes by Altera group [7] uses FPGA I/O pads with low-voltage differential signalling (LVDS) as a comparator. The differential input pin is faster in comparison with single ended input pin when used as a comparator.…”

Low Complexity System on Chip Design to Acquire Signals from MOS Gas Sensor Applications

“…This is more complex, but it can be used for analog input signals of up to 50 kHz. In [ 20 ], a 12-bit sigma-delta ADC similar to the one proposed in [ 19 ] is presented. The main difference between both proposals is that [ 20 ] uses an equalizer and a finite impulse response (FIR) filter apart from the CIC that adds more complexity to the design (700 LE-Logic Elements are required).…”

“…The main characteristic of these signals is their low frequency, so we do not need complex ADC techniques that include a CIC or an equalizer. The ADC proposed in the paper is based on the sigma-delta technique, but the CIC filters in [ 19 , 20 ] are substituted by a registered accumulator. The proposed solution is valid for low-frequency analog signals and allows a reduction in the complexity of the ADC.…”