Tall FIN formation for FINFET devices of 20nm and beyond using multi-cycles of passivation and etch processes

Abstract

In the past a few years, there has been a trend that non-planar field effect transistors (FETs) replace planar counterparts in semiconductor industry. One of critical and challenging processes to fabricate this non-planar device in bulk Si wafers is forming the array of tall Si fins with tight pitch that is used for gate channel as well as source and drain. Fin formation process typically involves deep Si etch using hard mask formed by double patterning technique (DPT). Traditional Si etch tends to results in intra-cell depth loading due to pitch walking and necking profile at the top portion of fins due to deep Si etch at small space. In addition, tall fins tend to stick to each other after post etch wet clean due to surface tension and hydrophilic fin sidewall. In this publication, 200nm tall fins with straight profile at the significant top portion of fins are demonstrated by using multi cycles of passivation and etch process. Physical and chemical parameters of each cycle were tuned respectively to generate straight top profile for gate channel control and smooth bottom profile to make it friendly for the following oxide gap fill process. Intra-cell and iso-dense depth loading is less than 3% of total depth. In addition, fin sticking is no longer observed after this multi cycle process. The exact mechanism is still under investigation but it is postulated that the fin sidewall surface condition has changed to be less hydrophilic due to multi cycle passivation.

The influence of post-etch InGaAs fin profile on electrical performance

“…3,14,15) With respect to the aspect ratio trapping technique, [16][17][18] which deposits the III-V fins from the bottom of the oxide trench, the dry etch process offers a top-down alternative similar to the conventional Si fin fabrication. [19][20][21][22] While the dry etch approach provides advantages such as process flexibility and simplicity, 23) it may also introduce complications at the etched surface, including stoichiometric or structure modification and atomic intrusion. 24,25) As a result, the electronic properties of InGaAs post etch could be modified.…”

Challenges of Tailoring Surface Chemistry and Plasma/Surface Interactions to Advance Atomic Layer Etching

“…[16][17][18] Furthermore, these recent concepts have been successfully commercialized and shown to reduce plasma damage and/or improve pattern fidelity. [19][20][21][22] Ironically, it is these same hardware enhancements that have set the stage to enable processing capability for atomic scale precision. Plasma pulsing, low electron temperature plasmas, pulsed gas flows etc., which are now incorporated into state of the art plasma processing toolsets are envisioned to be key advances to potentially enable ALE in a large scale production setting.…”