2022
DOI: 10.1109/mc.2022.3187847
|View full text |Cite
|
Sign up to set email alerts
|

Taming Memory With Disaggregation

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2

Citation Types

0
2
0

Year Published

2023
2023
2024
2024

Publication Types

Select...
3
1

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
(2 citation statements)
references
References 9 publications
0
2
0
Order By: Relevance
“…A similar design is memory expansion and pooling. The CXL protocol allows the CPU to share and address memory in the attached CXL device [28]. It can serve as a system-expansion interconnect, which runs on the Peripheral Component Interconnect Express (PCIe) bus with protocol-layer enhancements, that make it especially apt for memory attachment [28].…”
Section: Commercial Alternative Solutionsmentioning
confidence: 99%
See 1 more Smart Citation
“…A similar design is memory expansion and pooling. The CXL protocol allows the CPU to share and address memory in the attached CXL device [28]. It can serve as a system-expansion interconnect, which runs on the Peripheral Component Interconnect Express (PCIe) bus with protocol-layer enhancements, that make it especially apt for memory attachment [28].…”
Section: Commercial Alternative Solutionsmentioning
confidence: 99%
“…The CXL protocol allows the CPU to share and address memory in the attached CXL device [28]. It can serve as a system-expansion interconnect, which runs on the Peripheral Component Interconnect Express (PCIe) bus with protocol-layer enhancements, that make it especially apt for memory attachment [28]. It gives memory controllers the capability of implementing memory pooling, where a large amount of memory can be segmented into various regions which are then allocated to different PMs [11].…”
Section: Commercial Alternative Solutionsmentioning
confidence: 99%