Taming x86-TSO persistency

Abstract

We study the formal semantics of non-volatile memory in the x86-TSO architecture. We show that while the explicit persist operations in the recent model of Raad et al. from POPL'20 only enforce order between writes to the non-volatile memory, it is equivalent, in terms of reachable states, to a model whose explicit persist operations mandate that prior writes are actually written to the non-volatile memory. The latter provides a novel model that is much closer to common developers' understanding of persistency semantics. We further introduce a simpler and stronger sequentially consistent persistency model, develop a sound mapping from this model to x86, and establish a data-race-freedom guarantee providing programmers with a safe programming discipline. Our operational models are accompanied with equivalent declarative formulations, which facilitate our formal arguments, and may prove useful for program verification under x86 persistency.

Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores

“…The persistency semantics of wb memory has been previously formalised by Raad et al [2020b] and later refined in [Cho et al 2021;Khyzha and Lahav 2021]. As we describe shortly, wb memory follows relaxed, buffered persistency.…”

“…3a), while those on the same location persist in the store order. Following [Khyzha and Lahav 2021], we thus model the persistence buffer as a per-location map (PBMap in Fig. 13), associating each wb location x with a queue of persist-pending writes on x (PBuff in Fig.…”

“…On the hardware side, Raad and Vafeiadis [2018] developed a proposal for Intel-x86 persistency, which is rather different from the existing Intel-x86 model in [Intel 2021]. Raad et al [2020b] later formalised the persistency semantics of Intel-x86 as described in [Intel 2021], which was later refined in [Abdulla et al 2021;Cho et al 2021;Khyzha and Lahav 2021]. However, all three formal models covered the persistency semantics of wb memory alone, and excluded the other Intel-x86 memory types and non-temporal stores.…”

Abstraction for Crash-Resilient Objects (Extended Version)

“…This combination of features allows researchers and practitioners to develop a variety of efficient crash-resilient data structures (see, e.g., [12,29]). Recently, NVM has started to become available in commodity architectures of manufacturers such as Intel and ARM [4,21], and formal (operational and declarative) models of these systems have been proposed [9,23,28].…”

“…In this paper, we formulate and prove an abstraction theorem for concurrent programs utilizing non-volatile memory. We target the PSC ("Persistent Sequential Consistency") model of [23], which enriches the standard sequentially consistent shared-memory with non-volatile storage using per-location FIFO buffers to account for delayed and out-of-order persistence of writes. PSC constitutes a relatively simple model that is very close to developer's informal understanding of NVM.…”