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Chafi, Hassan; Minh, Chi Cao; McDonald, Austen; Carlstrom, Brian D.; Chung, JaeWoong; Hammond, Lance; Kozyrakis, Christos; Olukotun, Kunle

doi:10.1145/1088149.1088176

Cited by 18 publications

(6 citation statements)

References 27 publications

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“…• Hardware extensions for a simulated HTM system and a software API was suggested by the flagship HTM-only profiling work, TAPE [21]. It is useful for pinpointing and optimizing undesired HTM behaviors, but incurs some overhead due to API calls and saving profiling data to RAM.…”

Section: Contributionsmentioning

confidence: 99%

“…The The programming model of the underlying TMbox system [122] is comparable to the TCC model [54]. The monitoring techniques used in this work are in some parts similar to the TAPE [21] system. Major differences include the use of multiple ring buses in the TMbox system, compared to a switched bus network with different timing characteristics and influences on HTM behavior.…”

Section: Related Workmentioning

confidence: 99%

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A multicore emulator with a profiling infrastructure for transactional memory on FPGA

Sönmez

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This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memory environment on a multicore prototype that is realized on FPGA fabric. For this, we devise a MIPS-compatible shared-memory multicore emulator with Hybrid Transactional Memory support, based on the Plasma open source soft processor core. We present the design and implementation of the TMbox system, which features an emulation system of up to 16 soft processor cores interconnected with a bi-directional ring bus, running at 50 MHz on a Virtex5-155t FPGA. Additionally, we build the first comprehensive infrastructure to profile Hybrid TM systems, an extensive visualization environment that enables examining complete transactional executions in detail. TMbox is a completely modifiable architecture implementing a multicore prototype with support for STM, HTM and Hybrid TM. It was written in various common design languages, and enables modifying the complete stack, down from the ISA, through the software toolchain, up to the well-optimized parallel code. With such an infrastructure, fast execution and quick performance evaluation can be made possible for studies in computer architecture. En esta tesis se propone juntar dos temas recientes a través de la creación de un sistema de memoria transaccional en un circuito programable (un FPGA). Para ello, ha sido diseñado un emulador de multinúcleo, con soporte para memoria transaccional híbrida y núcleos MIPS basados en el procesador de código libre Plasma. Presentamos el diseño y la implementación del sistema TMbox, que implementa un sistema de emulación de hasta 16 núcleos MIPS interconectados con un bus en anillo bidireccional, funcionando a 50 MHz en un FPGA Virtex5-155t. Adicionalmente, hemos construido la primera infraestructura para perfilado y visualización de memoria transaccional híbrida, que permite ver con un alto detalle ejecuciones transaccionales completas. TMbox es una arquitectura completamente modificable, e implementa un prototipo de un multinúcleo con memoria transaccional en software, hardware e híbrido. Está compuesto de varios lenguajes de diseño muy comunes, y habilita modificar el stack completo, desde la ISA, pasando por el toolchain de software, hasta el código paralelo altamente optimizado. Con una infraestructura como TMbox, es posible la ejecución veloz y la evaluación rápida del rendimiento en investigaciones de arquitectura de computadores.

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Section: Contributionsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A multicore emulator with a profiling infrastructure for transactional memory on FPGA

Sönmez

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“…From their work, we were inspired that seeing the read set and write set of transactions can help to understand the reason for aborts. [23] for the Transactional Coherence and Consistency [24] system that has HTM support.…”

Section: Design and Implementationmentioning

confidence: 99%

“…Chafi et al developed the Transactional Application Profiling Environment (TAPE) which is a profiling framework for HTMs [23]. The raw results that TAPE produces can be used as input for the profiling techniques that we have proposed.…”

Section: Related Workmentioning

confidence: 99%

Programming, debugging, profiling and optimizing transactional memory programs

Hasanov Zyulkyarov

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Transactional memory (TM) is a new optimistic synchronization technique which has the potential of making shared memory parallel programming easier compared to locks without giving up from the performance. This thesis explores four aspects in the research of transactional memory. First, it studies how programming with TM compares to locks. During the course of work, it develops the first real transactional application ¿ AtomicQuake. AtomicQuake is adapted from the parallel version of the Quake game server by replacing all lock-based synchronization with atomic blocks. Findings suggest that programming with TM is indeed easier than locks. However the performance of current software TM systems falls behind the efficiently implemented lock-based versions of the same program. Also, the same findings report that the proposed language level extensions are not sufficient for developing robust production level software and that the existing development tools such as compilers, debuggers, and profilers lack support for developing transactional application. Second, this thesis introduces new set of debugging principles and abstractions. These new debugging principles and abstractions enable debugging synchronization errors which manifest at coarse atomic block level, wrong code inside atomic blocks, and also performance errors related to the implementation of the atomic block. The new debugging principles distinguish between debugging at the language level constructs such as atomic blocks and debugging the atomic blocks based on how they are implemented whether TM or lock inference. These ideas are demonstrated by implementing a debugger extension for WinDbg and the ahead-of-time C# to X86 Bartok-STM compiler. Third, this thesis investigates the type of performance bottlenecks in TM applications and introduces new profiling techniques to find and understand these bottlenecks. The new profiling techniques provide in-depth and comprehensive information about the wasted work caused by aborting transactions. The individual profiling abstractions can be grouped in three groups: (i) techniques to identify multiple conflicts from a single program run, (ii) techniques to describe the data structures involved in conflicts by using a symbolic path through the heap, rather than a machine address, and (iii) visualization techniques to summarize which transactions conflict most. The ideas were demonstrated by building a lightweight profiling framework for Bartok-STM and an offline tool which process and display the profiling data. Forth, this thesis explores and introduces new TM specific optimizations which target the wasted work due to aborting transactions. Using the results obtained with the profiling tool it analyzes and optimizes several applications from the STAMP benchmark suite. The profiling techniques effectively revealed TM-specific bottlenecks such as false conflicts and contentions accesses to data structures. The discovered bottlenecks were subsequently eliminated with using the new optimization techniques. Among the optimization highlights are the transaction checkpoints which reduced the wasted work in Intruder with 40%, decomposing objects to eliminate false conflicts in Bayes, early release in Labyrinth which decreased wasted work from 98% to 1%, using less contentions data structures such as chained hashtable in Intruder and Genome which have higher degree of parallelism.

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“…• Hardware extensions for a simulated HTM system and a software API was suggested by the flagship HTM-only profiling work, TAPE [50]. It is useful for pinpointing and optimizing undesired HTM behaviors, but incurs some overhead due to API calls and saving profiling data to RAM.…”

Section: Introductionmentioning

confidence: 99%

Multicore architecture prototyping on reconfigurable devices

Arcas Abella

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In the the last decades several performance walls were hit. The memory wall and the power wall are limiting the performance scaling of digital microprocessors. Homogeneous multicores rely on thread-level parallelism, which is challenging to exploit. New heterogeneous architectures promise higher performance per watt rates, but software simulators have limited capacity to research them. In this thesis we investigate the advantages of Field-Programmable Gate Array devices (FPGA) for multicore research. We developed three prototypes, implementing up to 24 cores in a single FPGA, showing their superior performance and precision compared to software simulators. Moreover, our prototypes perform full-system emulation and are totally modifiable. We use our prototypes to implement novel architectural extensions such as Transactional Memory (TM). This use case allowed us to research different needs that computer architects may have, and how to implement them on FPGAs. We developed several techniques to offer profiling, debugging and verification techniques in each stage of the design process. These solutions may bridge the gap between FPGA-based hardware design and computer architects. In particular, we place a special stress on non-obtrusive techniques, so that the precision of the emulation is not affected. Based on the current trends and the sustained growth in the high-level synthesis community, we expect FPGAs to become an integral part of computer architecture design in the next years. En les darreres dècades s'ha xocat amb diversos "murs" de rendiment. El mur de la memòria i el mur de la potència estan limitant l'escalat del rendiment dels microprocessadors digitals. Els multiprocessadors homogenis depenen del paral·lelisme a nivell de fil d'execució, el qual és difícil de rendibilitzar. Les noves arquitectures heterogènies prometen més rendiment per watt, però els simuladors de software tenen una capacitat limitada per investigar-les. En aquesta tesi investiguem els avantatges de les Field-Programmable Gate Arrays (FPGA, o matrius de portes programables in situ) per a investigació sobre multiprocessadors. Hem desenvolupat tres prototipus que implementen fins a 24 nuclis en una sola FPGA, mostrant els seus rendiment i precisió superiors als dels simuladors de software. A més, els nostres prototipus realitzen emulació del sistema complet i són completament modificables. Hem utilitzat els nostres prototipus per implementar noves extensions arquitectòniques com la Transactional Memory (TM, o memòria transaccional). Aquest cas d'ús ens ha permès investigar les necessitats que els arquitectes de computadors poden tenir, i com implementar-les en una FPGA. Hem desenvolupat diverses tècniques que ofereixen traces, depuració i verificació en cada etapa del procés de disseny. Aquestes solucions poden reduir l'escletxa entre els simuladors basats en FPGA i els arquitectes de computadors. En concret, hem posar especial èmfasi en tècniques que no interfereixin amb l'execució, per tal que la precisió de la simulació no es vegi afectada. A partir de les tendències actuals i l'augment sostingut de la comunitat de síntesis d'alt nivell, preveiem que les FPGA esdevindran una part integral del disseny d'arquitectures de computadors en els propers anys.

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Tape

Cited by 18 publications

References 27 publications

A multicore emulator with a profiling infrastructure for transactional memory on FPGA

A multicore emulator with a profiling infrastructure for transactional memory on FPGA

Programming, debugging, profiling and optimizing transactional memory programs

Multicore architecture prototyping on reconfigurable devices

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