TaPEr

Abstract

A new challenge in multicore design is the management of dark silicon. Among the on-chip components, the cores and caches consume most of the power. We observe that parallel programs exhibit different scalability characteristics with respect to the number of cores and the size of caches. Running programs with fewer cores or smaller caches does not always degrade performance significantly. Based on these observations, we propose a scheme, called TaPEr, that can dynamically (1) predict the scalability of parallel programs with respect to core count and cache capacity; (2) re-allocate available power to cores or caches based on a program's scalability in order to satisfy the power constraints; and (3) achieve high performance (comparing with DVFS or simple shutdown schemes) at the same time.