Tapered Through-Silicon-Via Interconnects for Wafer-Level Packaging of Sensor Devices

Leib, J.; Bieck, Florian; Hansen, Ulli; Looi, Kok-Kheong; Ngo, Ha-Duong; Seidemann, V.; Shariff, Dzafir; Studzinski, Daniel; Suthiwongsunthorn, Nathapong; Tan, Kenneth; Wilke, Ralph; Yam, Kwong-Loon; Topper, Michael J.

doi:10.1109/tadvp.2009.2026950

Cited by 12 publications

(6 citation statements)

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“…Such problems can be solved by etching tapered vias using laser ablation or DRIE [210], [211], which facilitates both deposition and patterning. Maskless laser ablation is actually a quite convenient way to pattern the SiO 2 /polymer layer deposited on the via base.…”

Section: Strategy For Tsv In Mems Chipsmentioning

confidence: 99%

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Wang

2015

J. Microelectromech. Syst.

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After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore's Law without needing to continuously shrink feature sizes. The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics. This 3-D heterointegration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications. This paper reviews the following aspects of the MEMS/ microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/ microsensor products using 3-D integration technologies. Of particular interest throughout this paper is the heterointegration of the MEMS and CMOS technologies. [2015-0158]Index Terms-Three-dimensional (3-D) integration, microelectromechanical systems (MEMS), microsensor, packaging, hetero-integration, interposer, through-silicon-via (TSV), waferlevel packaging, microsystem.

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Section: Strategy For Tsv In Mems Chipsmentioning

confidence: 99%

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Wang

2015

J. Microelectromech. Syst.

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“…To meet the urgent market demand of small package size and high reliability performance for automotive CIS application, wafer level chip scale packaging (WLCSP) technology, using through silicon vias (TSV), needs to be developed to replace current chip on board (COB) packages [ 19 , 20 , 21 , 22 ]. Three-dimensional WLCSP with TSV technology takes advantages in shorter electrical interconnection, small form factor, high yield, and low cost [ 23 , 24 , 25 , 26 , 27 , 28 ].…”

Section: Introductionmentioning

confidence: 99%

“…Previous works have focused on package fabrication, rather than reliability performance. The structure they introduced suffered different failure modes in reliability tests, such as pad delamination [ 21 ] and oxide crack [ 22 ], which were unacceptable in automotive application.…”

Section: Introductionmentioning

confidence: 99%

Development of Reliable, High Performance WLCSP for BSI CMOS Image Sensor for Automotive Application

Zhou

Ma²,

et al. 2020

Sensors

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To meet the urgent market demand for small package size and high reliability performance for automotive CMOS image sensor (CIS) application, wafer level chip scale packaging (WLCSP) technology using through silicon vias (TSV) needs to be developed to replace current chip on board (COB) packages. In this paper, a WLCSP with the size of 5.82 mm × 5.22 mm and thickness of 850 μm was developed for the backside illumination (BSI) CIS chip using a 65 nm node with a size of 5.8 mm × 5.2 mm. The packaged product has 1392 × 976 pixels and a resolution of up to 60 frames per second with more than 120 dB dynamic range. The structure of the 3D package was designed and the key fabrication processes on a 12” inch wafer were investigated. More than 98% yield and excellent optical performance of the CIS package was achieved after process optimization. The final packages were qualified by AEC-Q100 Grade 2.

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“…Compared to traditional wire-bonding methods, through-silicon vias (TSVs) provide a short interconnect path with a high density [1,2]. Therefore, in recent years conductive TSVs have become an important emerging technology for electrical connection of stacked devices in semiconductor industry as alternative to conventional wire bonding [1] and to connect and control stacked MEMS or combined MEMS-CMOS modules in order to save space (see Fig.…”

Section: Introductionmentioning

confidence: 99%