Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation

Abstract

Abstract:As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools for handling SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach for addressing system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC co-design framework: Gaspard2. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented works are based on Model-Driven Engineering and the UML MARTE profile proposed by Object Management Group, for modeling and analysis of real-time embedded systems. Our contributions thus relate to presenting a complete design flow to move from high level MARTE models to automatic code generation, for implementation of dynamically reconfigurable SoCs.

Adaptivity in high-performance embedded systems: a reactive control model for reliable and flexible design

“…In addition to functional specification, this control model is also adopted in IP deployment for reconfigurable FPGAs, which is detailed in Quadri et al (2010).…”

Model‐driven physical‐design automation for FPGAs: fast prototyping and legacy reuse

“…These profiles allow the specification of systems using high‐level models that can be automatically (or semi‐automatically) transformed to low‐level hardware description languages, such as VHDL. In , for example, the authors propose an HLS and design space exploration flow based on the MDE methodology, which, based on successive refinements of a high‐level model, generates VHDL hardware accelerators.…”

FPGA physical-design automation using Model-Driven Engineering

“…VHDL) code is generated by mapping UML concepts with the target language syntax. In [8], [9], for example, the authors propose a HLS and design space exploration flow based on the MDE methodology, which based on successive refinement of the high-level model generates VHDL hardware accelerators.…”

“…While, during the last years, the model-driven engineering (MDE) [7] methodology has been adopted as a generic and scalable solution for application high-level synthesis (HLS), in the context of SoC [8], hardware accelerator design [9] and embedded systems in general. At the physical design level, to the best of our knowledge, there are no tools using this methodology.…”